SOYO SY-5SSM/5 manual Chipset Features Setup

BIOS Setup Utility		SY-5SSM & SY-5SSM/5
CHIPSET FEATURES SETUP
CHIPSET	Setting	Description	Note
FEATURES

Ref/Act Command Delay

6T Set the DRAM clock of the Default 5T,7T, 8T refresh command to

refresh/active command delay.

Refresh Queue Depth

RAS Precharge Time

RAS to CAS Delay

12	Set the depth of refresh	Default
0, 4, 8,	queue.
3T	The precharge time is the	Default
2T, 4T, 5T	number of cycles it takes for
	the RAS to accumulate its
	charge before DRAM
	refreshes. If insufficient time
	is allowed, refresh may be
	incomplete and the DRAM
	may fail to retain data.
3T	When DRAM is refreshed,	Default
2T,4T,5T	both rows and columns are
	addressed separately. This
	setup item allows you to
	determine the timing of the
	transition from RAS (row

address strobe) to CAS (column address strobe).

CPU to PCI Burst Mom. WR

Disabled	Select enabled permits PCI
Enabled	burst memory write cycles,	Default
	for faster performance.

When disabled, performance is slightly slower, but more reliable.

CPU to PCI Post Write

Disabled	Select enabled to use a fast
Enabled	buffer for posting writes to	Default
	memory. Using a fast

buffer releases the CPU before completion of a write cycle to DRAM.

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