Spectrum Brands MI.20xx Hardware information

Introduction Hardware information

(c) Spectrum GmbH 11

Hardware information

Block diagram

Technical Data

Resolution 8 bit Dimension 312 mm x 107 mm

Differential linearity error (ADC) 0.5 LSB typ. Width (Standard) 1 full size slot

Integral linearity error (ADC) 0.5 LSB typ. Width (with star hub option) 2 full size slots

Multi: Trigger to 1st sample delay fixed Analogue Connector 3 mm SMB male

Multi: Recovery (re-arm) time < 20 samples Overvoltage protection (range < ±500 mV) ±5 V

Trigger accuracy 2/4 channel mode 1 Sample Overvoltage protection (range > ±500 mV) ±50 V

Trigger accuracy 1 channel mode 2 Samples Warm up time 10 minutes

Ext. clock: delay to internal clock 42 ns ± 2 ns Operating temperature 0°C - 50°C

input signal with 50 ? termination max 5 V rms Storage temperature -10°C - 70°C

Trigger output delay 1 Sample Humidity 10% to 90%

Input impedance 50 Ohm / 1 MOhm || 25 pF

Min internal clock 1 kS/s Power consumption 5 V @ full speed max 3.4 A (17.0 Watt)

Min external clock 1 MS/s Power consumption 5 V @ power down max 1.9 A (9.5 Watt)

Trigger input:Standard TTL level Low: -0.5 > level < 0.8 V

High: 2.0 V > level < 5.5 V

Trigger pulse must be valid > 2 clock periods.

Clock input: Standard TTL level Low: -0.5 > leve l < 0.8 V

High: 2.0 V > level < 5.5 V

Rising edge is used.

Required duty cycle: 50% ± 5%

Trigger output Standard TTL, capable of driving 50 Ohm.

Low < 0.4 V (@ 20 mA, max 64 mA)

High > 2.4 V (@ -20 mA, max -32 mA)

One positive edge after the first internal trigger

Clock output Standard TTL, capable of driving 50 Ohm

Low < 0.4 V (@ 20 mA, max 64 mA)

High > 2.4 V (@ -20 mA, max -32 mA)

Input range ±50 mV ±100 mV ±200 mV ±500 mV ±1 V ±2 V ±5 V

Software programmable offset ±200 mV ±400 mV ±800 mV ±2 V ±4 V ±8 V ±20 V

Offset error < 1 LSB, adjustable by user

Gain error < 2 %< 2 %< 2 %< 2 %< 2 %< 2 %< 2 %

MI.202x: Noise (rms): 50 Ohm, 50 MS/s < 0.5 LSB < 0.5 LSB < 0.5 LSB < 0.5 LSB < 0.5 LSB < 0.5 LSB < 0.5 LSB

MI.203x: Noise (rms): 50 Ohm, 100/200 MS/s < 2.0 LSB < 1.5 LSB < 1.0 LSB < 1.0 LSB < 1.0 LSB < 1.0 LSB < 1.0 LSB

Crosstalk 5 MHz signal, ±50 mV input, 50 Ohm < 62 dB

Contents

Main Page Page Page Page Introduction Preface General Information Different models of the MI.20xx series Additional options Extra I/O (Option -XMF) Extra I/O (Option -XIO) Starhub Timestamp The Spectrum type plate Introduction Hardware information (c) Spectrum GmbH 11 Hardware information Block diagram Technical Data 12 MI.20xx Manual Hardware information Introduction Dynamic Parameters Order information Hardware Installation System Requirements Warnings ESD Precautions Cooling Precautions Installing a board with digital inputs/outputs Installing a board with extra I/O (Option -XMF) Installing multiple boards synchronized by starhub Installing multiple synchronized boards Software Driver Installation Interrupt Sharing Windows 98 Page Windows 2000 Page Windows XP Page Windows NT Adding boards to the Windows NT driver Linux Overview Page Software Software Overview First Test with SBench C/C++ Driver Interface Header files Microsoft Visual C++ Linux Gnu C Other Windows C/C++ compilers National Instruments LabWindows/CVI Page Page Delphi (Pascal) Programming Interface Type definition Include Driver Examples Page Visual Basic Programming Interface Include Driver Visual Basic Examples VBA for Excel Examples Page Programming the Board Register tables Programming examples Error handling Initialization Starting the automatic initialization routine PCI Register Hardware version Date of production Serial number Maximum possible sample rate Installed memory Installed features and options Used interrupt line Used type of driver Powerdown and reset Analog Inputs Channel Selection Important note on channels selection Setting up the inputs Input ranges Input offset Input termination Automatical adjustment of the offset settings Standard acquisition modes General Information Programming Memory, Pre- and Posttrigger Starting without interrupt (classic mode) Starting with interrupt driven mode Data organization Sample format Reading out the data with SpcGetData Page FIFO Mode General Information Background FIFO Read Speed Limitations Programming Software Buffers Buffer processing FIFO mode Example FIFO acquisition mode Data organization Sample format Clock generation Internally generated sample rate Standard internal sample rate Using plain quartz with no PLL External reference clock External clocking Direct external clock Page External clock with divider Trigger modes and appendant registers General Description Software trigger External TTL trigger Edge triggers Pulsewidth triggers Page Channel Trigger Overview of the channel trigger registers Triggerlevel Page Detailed description of the channel trigger modes Page Page Page Page Page Page Page Option Multiple Recording Recording modes Standard Mode FIFO Mode Trigger modes Trigger modes Option Multiple Recording Resulting start delays Option Gated Sampling Recording modes Standard Mode FIFO Mode Trigger modes Allowed trigger modes Example program Option Timestamp General information Timestamp modes Standard mode StartReset mode Timestamp Status Reading out timestamp data Functions for accessing the data Data format Option Timestamp Example programs Example programs Standard acquisition mode Acquisition with Multiple Recording Option Extra I/O Digital I/Os Channel direction Transfer Data Analog Outputs Programming example Synchronization (Option) The different synchronization options Synchronization with option cascading Synchronization with option starhub The setup order for the different synchronization options Setup Order for use with standard (non FIFO) mode and equally clocked boards Page Page Page Setup synchronization for use with FIFO mode and equally clocked boards Page Additions for synchronizing different boards SumSampleRateNSampleRate=NActChPerModuleN SyncSpeed Page Additions for equal boards with different sample rates Resulting delays using different boards or speeds = ResultingDelay ClockMasterDelay ClockSlaveDelayN 94 MI.20xx Manual Appendix Error Codes Pin assignment of the multipin connector Extra I/O with external connector(Option -XMF) Pin assignment of the multipin cable Pin assignment of the internal multipin connector Extra I/O with internal connector (Option -XIO)