Thales Computers 2-9 CPMC-1553R User’s Guide, CA.DT.356-0e
2.2.2.2 ACE Configuration and User I/O Register The ACE configuration used on the board can be read
via PCI I/O space defined in BAR1, with an address offset of 0x0800. In addition, this register also
provides the means for software to read the eight input bits and control the eight, open-drain output bits.
The output bits are pulled to 5V using 4.7K ohm resistors. This register is defined in Table 8.
Table 8. Signal Definition of Address 0x800, BAR 1
Data Bit Read/Write Definition
31..24 Read/Write User defined outputs 7..0. After a PCI reset all
outputs are not driven.
23..16 Read User defined inputs 7..0
15..12 Not used Always returns the value 0x0
11 Read 0 – 64kB x 16 Mini-ACE
1 – 4kB x 16 Mini-ACE
10..8 Read Indicates the number of mini-ACE devices
000 – 1 Mini-ACE
001 – 2 Mini-ACEs
7..3 Read Always returns the value 0x1F.
2 Read 0 – User defined I/O interrupt active
1 – User defined I/O interrupt inactive
Check which input bit generated the interrupt by
reading the Interrupt Control and Status register.
1..0 Read 0 - Mini-ACE[2..1] interrupt active
1 - Mini-ACE[2..1] interrupt inactive
2.2.2.3 Interrupt Control/Status Register Each of the input bits can be independently configured to
generate an input based on a rising edge, falling edge, or either edge. The inputs are “debugged” using a 90
nanosecond digital filter before being applied to the edge detectors. A PCI reset clears the register.
Table 9. Interrupt Control/Status Register at 0x0804, BAR1
Data Bit Read/Write Definition
31..24 Read/Write 1 – Enable falling edge interrupt on input 7..0
0 – Inhibit falling edge interrupt on input 7..0
23..16 Read/Write 1 – Enable rising edge interrupt on input 7..0
0 – Inhibit rising edge interrupt on input 7..0
15..8 Read
Write
1 – Falling edge interrupt detected on input 7..0
0 - Falling edge interrupt not detected on input 7..0
1 – Clear falling edge interrupt status on input 7..0
0 – Do not change interrupt status for input 7..0
7..0 Read
Write
1 – Rising edge interrupt detected on input 7..0
0 - Rising edge interrupt not detected on input 7..0
1 – Clear rising edge interrupt status on input 7..0
0 – Do not change interrupt status for input 7..0