Chapter 2: Overview

2-11

2-2 Chipset Overview
Built upon the functionalit y and the capability of the Intel 5 520 platform, the X8DTU-
LN4F+ motherboard provides the p erformance and feature s et s required for dual-
processor-based high- en d systems an d HPC /Cluste r ser ver s. The 5 520 plat fo rm
consists of the 5500/ 560 0 Serie s (LGA 1366) proc essor, the 36 D IOH (IO Hu b),
and the ICH10R (South Bridge). With the Intel Qui ck Path inte rc onne ct (QPI) c on -
troller built in, the 5500 /5600 Series Proce ssor is the fi rst dual-processing platform
that offers the next generation point-to-point system interconnect interface which
will greatly enhance system per fo rmanc e by utiliz ing ser ial link inte rcon necti ons,
allowing for increased band width a nd sca labili ty.
The IOH connects to each pro cessor through an independent Q uickPath Intercon-
nect (QPI) link. Each link consists of 20 pairs of unidirectional differential lanes
for data transmission in ad di t io n t o a di f ferential forwarded c l o c k . A f u ll -width QPI
link pair provides 84 signals. Each processor supports two QuickPath links, one
going to the other processor a nd the oth er to the 3 6D IO H ub.
The 5520 chipset support s up to 36 P CI Expr ess Ge n2 lanes , peer-to -pe er read
and write transactions . The ICH10R provides up to six P CI-Expres s ports, six
SATA ports and eight USB connections .
In addition, the 5520 chipset al so offer s a wide range o f RAS (Reli ability, Avail-
ability and Serviceab ility) features. These features includ e memory interface ECC,
x4/x8 Single Device Data Co rrect ion (SDDC), Cyc lic Redunda ncy Check (CRC),
parity protection, out- of- ba nd reg ister ac c ess v ia SM Bus, m emo r y mir ror ing, a nd
Hot-plug support on the P CI- E xpres s Inter fac e.

Main Features of the 5500/5600 Series Processor and the

5520 Chipset

Four processor cores in each processor with 8MB shared cache among cores•
Two full-width Intel QuickPath interconnect (QPI) links, up to 6.4 GT/s of data •
transfer rate in each direction
Virtualization Technology, Integrated Management Engine supported
•
Point-to-point cache coherent interconnect, fast/narrow unidirectional links, and •
concurrent bi-directional traffi c
Error detection via CRC and error correction via Link-level retry
•