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Texas Instruments TA5704EVM Spdif Receiver, Engineering Evaluation Only, Spdif Format, DIR9001PW

Models: TA5704EVM

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SPDIF RECEIVER			ENGINEERING EVALUATION ONLY
							SPDIF
							LOCK
	U2
RCA INPUT	SPDIF FORMAT
	DATA FORMAT	FMT1 FMT0
	16Bit/MSB/RJ	L	L
	24Bit/MSB/RJ	L	H
	24Bit/MSB/LJ	H	L
OPTO INPUT	24Bit/MSB/I2S	H	H
OPTO INPUT
	SHUNTS IN = 0			JUMPER NOTES
	SHUNTS OUT = 1			JUMPER NOTES
	SHUNTS OUT = 1		1-2: SPDIF CLOCKS/DATA
			1-2: SPDIF CLOCKS/DATA				TO
			2-3: CLOCKS/DATA = PSIA				TO
	DIR9001PW				(MCLK)		TAS5704
					(MCLK)

JP1 IN: SCKO = 512 Fs					(SDATA)
JP1 IN: SCKO = 512 Fs
JP1 OUT: SCKO = 256 Fs (DEFAULT)					(SCLK)
					(SCLK)
					(LRCLK)
SPDIF
INPUT			JUMPER NOTES
SELECT			JUMPER NOTES				TO
1-2: OPTO INPUT			1-2: SPDIF CLOCKS/DATA (DEFAULT)				ADC
2-3: COAX INPUT			2-3: CLOCKS/DATA = PSIA
OPTO
INPUT
COAX
INPUT
FROM MASTER RESET
DECOUPLING	DECOUPLING
			CX PROJECT: TAS5704 EVALUTION MODULE
			Design Team:	RYAN KEHR
			Schematic Rev:	NC	Mod: NC	PCB Rev: NC Sheet	1 of 6
			Save Date: JULY 10, 2007			Print Date Tue Jul 10, 2007
	TIFilename: TAS5704EVM.SCH						Drawn By: LDN

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Texas Instruments TA5704EVM Spdif Receiver, Engineering Evaluation Only, Spdif Format, CX PROJECT TAS5704 EVALUTION MODULE

Contents

Users Guide Literature Number SLOU224 AprilSLOU224-April2008 Submit Documentation FeedbackContents List of Figures List of TablesRead This First PrefaceHow to Use this Manual About This ManualAdditional Documentation EVM Warnings / Restrictions and FCC WarningAdditional Documentation Read This FirstUsers Guide 1Overview1.1TAS5704EVM Features Figure 3. 4-ChannelSE Configuration1.2Basic Tools for Initial Board Power up 2System Interfaces2.1PSU Interface Figure 4. Top Composite View of TAS5704EVM2.4Digital Audio Interface SPDIF J1/OPTO 2.2PSC ConnectorTable 1. Recommended Power Supplies 2.6Board Power up General Guidelines 2.5ADC Interface3 Jumpers and Control Utilities 3.1Clock Frequency Change Jumper3.6CONFIG Jumpers Table 3. TAS5704 Gain Configuration3.4GAIN Jumpers 3.5Data Format Jumpers3.7Switches Table 6. TAS5704 Output Configuration4 Board Layout, Bill of Material, and Schematics Board Layout, Bill of Material, and Schematics4.1TAS5704EVM Board Layout, Top Composite View Figure 5. Top Layer CompositeBoard Layout, Bill of Material, and Schematics 4.2TAS5704EVM Board Layout, Top Layer ViewFigure 6. Top Layer Submit Documentation FeedbackBoard Layout, Bill of Material, and Schematics 4.3TAS5704EVM Board Layout, Bottom Layer ViewFigure 7. Bottom Layer Submit Documentation FeedbackBoard Layout, Bill of Material, and Schematics 4.4Bill of MaterialsTable 7. Bill of Materials for TAS5704EVM Submit Documentation FeedbackSubmit Documentation Feedback Board Layout, Bill of Material, and SchematicsSLOU224-April2008 4.5Schematic The schematics are appended to this documentBoard Layout, Bill of Material, and Schematics Submit Documentation FeedbackSPDIF RECEIVER ENGINEERING EVALUATION ONLYSPDIF FORMAT CX PROJECT TAS5704 EVALUTION MODULEANALOG TO DIGITAL CONVERTER 1-2 SDIN2 = ADC DEFAULTSchematic Rev ENGINEERING EVALUATION ONLYMASTER RESET TAS5704 I/OENGINEERING EVALUATION ONLY TAS5704PAPPOWER SUPPLIES SUBWOOFER CONNECTORBOM ONLY POWER INPUTSREVISION CHANGES REVISIONDESCRIPTION DATEENGINEERING EVALUATION ONLY TEXAS INSTRUMENTS DISCLAIMERDISCLAIMER EVM WARNINGS AND RESTRICTIONS EVALUATION BOARD/KIT IMPORTANT NOTICEFCC Warning Applications IMPORTANT NOTICEProducts

SPDIF RECEIVER

ENGINEERING EVALUATION ONLY

SPDIF FORMAT

DIR9001PW

CX PROJECT: TAS5704 EVALUTION MODULE