SPDIF RECEIVER

 

 

ENGINEERING EVALUATION ONLY

 

 

 

 

 

 

 

SPDIF

 

 

 

 

 

 

 

LOCK

 

U2

 

 

 

 

 

 

RCA INPUT

SPDIF FORMAT

 

 

 

 

 

 

DATA FORMAT

FMT1 FMT0

 

 

 

 

 

16Bit/MSB/RJ

L

L

 

 

 

 

 

24Bit/MSB/RJ

L

H

 

 

 

 

 

24Bit/MSB/LJ

H

L

 

 

 

 

OPTO INPUT

24Bit/MSB/I2S

H

H

 

 

 

 

 

 

 

 

 

 

 

 

SHUNTS IN = 0

 

JUMPER NOTES

 

 

SHUNTS OUT = 1

 

 

 

1-2: SPDIF CLOCKS/DATA

 

 

 

 

TO

 

 

 

2-3: CLOCKS/DATA = PSIA

 

DIR9001PW

 

 

 

(MCLK)

TAS5704

 

 

 

 

 

 

 

 

 

 

 

 

JP1 IN: SCKO = 512 Fs

 

 

 

 

(SDATA)

 

 

 

 

 

 

 

 

JP1 OUT: SCKO = 256 Fs (DEFAULT)

 

 

 

 

(SCLK)

 

 

 

 

 

 

 

 

 

 

 

 

(LRCLK)

 

SPDIF

 

 

 

 

 

 

 

INPUT

 

 

JUMPER NOTES

 

 

SELECT

 

 

 

TO

1-2: OPTO INPUT

 

 

1-2: SPDIF CLOCKS/DATA (DEFAULT)

ADC

2-3: COAX INPUT

 

 

2-3: CLOCKS/DATA = PSIA

 

 

OPTO

 

 

 

 

 

 

 

INPUT

 

 

 

 

 

 

 

COAX

 

 

 

 

 

 

 

INPUT

 

 

 

 

 

 

 

FROM MASTER RESET

 

 

 

 

 

 

 

DECOUPLING

DECOUPLING

 

 

 

 

 

 

 

 

 

CX PROJECT: TAS5704 EVALUTION MODULE

 

 

 

Design Team:

RYAN KEHR

 

 

 

 

 

Schematic Rev:

NC

Mod: NC

PCB Rev: NC Sheet

1 of 6

 

 

 

Save Date: JULY 10, 2007

Print Date Tue Jul 10, 2007

 

TIFilename: TAS5704EVM.SCH

 

Drawn By: LDN

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Texas Instruments TA5704EVM manual Spdif Receiver