Texas Instruments TAS5103EVM, TAS5102 manual J1 Amplifier Connection to MC012 Controller Module

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The recommended TAS5102/3 power-up sequence is shown in Figure 4. For proper TAS5102/3 operation, the RESET signal should be kept low during power up. RESET is pulled low during power up for 200 ms by the onboard reset generator (U2).

System￿power￿supply

Output￿stage￿power￿supply

RESET

>1￿ms

Figure 4. Recommended Power-Up Sequence

4.2J1 Amplifier Connection to MC012 Controller Module

Table 4. J9/J10 Pin Description Amplifier/Controller Connector

Pin No.	Net-Name at
	Schematics
1, 2, 5, 6 ,10, 11, 28	DGND
3, 4	PVDD1
7	OTW

8, 9, 13, 15, 17, 19, 20, 21,	NC
22, 23, 25, 27

Description

Low-current ground for modulator/controller

PVDD buffered through 24-Ωresistor to power the modulator/controller Overtemperature warning from the amplifier (T > 125°C)

Not connected

12	PWM_A	Channel A PWM signal from modulator
14	PWM_B	Channel B PWM signal from modulator
16	PWM_C	Channel C PWM signal from modulator
18	PWM_D	Channel D PWM signal from modulator
24	RESET	Resets the TAS5102/3
26	FAULT	Power stage fault indicator

4.3 Loudspeaker Connectors (J3 - J6)

CAUTION

Both positive and negative speaker outputs are floating and may not be connected to ground (e.g., through an oscilloscope).

	Table 5. Output Pin Description
Net-Name at Schematics	Description
OUT_A	Speaker positive output
OUT_B	Speaker negative output
OUT_C	Speaker positive output
OUT_D	Speaker negative output

10	TAS5102EVM and TAS5103EVM for the TAS5102 and TAS5103 Digital Amplifier Power Output Stages	SLLU106–August 2008
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