Texas Instruments TAS5518 manual 2.6Digital Audio Interface J60, 8.J60 Pin Description

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Digital Audio Interface (J60)

2.6Digital Audio Interface (J60)

The digital audio interface contains digital audio signal data (I2S), clocks, etc. Please refer to the TAS5518 Data Manual for signal timing and details not covered in this document.

		Table 2-8. J60 Pin Description
PIN	NET NAME
	AT	DESCRIPTION
NO.
	SCHEMATICS
1, 3, 10,	GND	Ground
12, 14, 16
2	MCLK	Master clock input. Low-jitter system clock for PWM generation and reclocking. Ground connection
		from source to the TAS5518 must be a low-impedance connection.
3	GND	Ground
4	SDIN1	I2S data 1, channel 1 and 2
5	SDIN2	I2S data 2, channel 3 and 4
6	SDIN3	I2S data 3, channel 5 and 6
7	SDIN4	I2S data 4, channel 7 and 8
8, 9, 15	—	Reserved
11	SCLK	I2S bit clock
13	LRCLK	I2S left-right clock

16 System Interfaces SLEU074 –June 2006

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