Transcend Information TS16GSSD25S-M, TS128GSSD25S-M, TS8GSSD25S-S Power on sequence timing diagram

TS8GSSD25S-S
TS16GSSD25S-S/M
TS32GSSD25S-S/M
TS64GSSD25S-S/M
TS128GSSD25S-M	2.5” Solid State Disk
TS192GSSD25S-M

5.Host locks – after detecting the COMWAKE, the host starts transmitting D10.2 characters at its lowest supported rate. Meanwhile, the host receiver locks to the ALIGN sequence and, when ready, returns the ALIGN sequence to the device at the same speed as received. A host shall be designed such that it acquires lock in 54.6 us (2048 nominal Gen1 Dword times) at any given speed. The host should allow for at least 873.8 us (32768 nominal Gen1 Dword times) after detecting the release of COMWAKE to receive the first ALIGNP. This ensures interoperability with multi-generational and synchronous designs. If no ALIGNP is received within 873.8 us (32768 nominal Gen1 Dword times) the host restarts the power-on sequence – repeating indefinitely until told to stop by the Application layer. 6. Device locks – the device locks to the ALIGN sequence and, when ready, sends SYNCP indicating it is ready to start normal operation.

6.Upon receipt of three back-to-back non-ALIGNPprimitives, the communication link is established and normal operation may begin.

Power on sequence timing diagram

The following timing diagrams and descriptions are provided for clarity and are informative.

	Figure 7 : power on sequence
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V1.08