Epson 6200A manuals
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97 pages 543.32 Kb
NOTICE 2 SEIKO EPSON CORPORATION 2001, All rights reserved.3 Configuration of product numberDevices S1 C 60N01 F 0A01 Development tools S5U1 C 60R08 D1 1 00 5 S1C6200/6200A Core CPU ManualCONTENTS 1D 2M 3I B. INSTRUCTION INDEX ______________________________________ 87 7 1D 1.1 System Features 1.2 Instruction Set Features 1.3 Differences between S1C6200 and S1C6200A1 DESCRIPTION 8 S1C6200 CORE CPU8-bit address bus13-bit address bus Fig. 1.1 Block diagram4-bit data busS1C6200/6200A CORE CPU MANUAL EPSON 3 9 2M Fig. 2.1.1 Program memory configuration 2.1 Program Memory (ROM)PCP PCS (within bank) 12-bit instructions Program or data code area Program or data code or CALZ subloutines in Bank 0 Program or data code or CALZ subloutines in Bank 1 10 2.1.1 Program counter block2.1.2 Flags 11 2.1.3 Jump instructions2.1.4 PSET with jump instructions 2.1.5 Call instructions 12 2.1.6 PSET instruction2.1.7 CALZ instructionFig. 2.1.7.1 The use of the CALZ instruction Bank 0 Page 0EEE.................... RET Bank 0 Page 2PSET CALZ LD Not effect on destination of CALZ 0AH EEE A,0S1C6200/6200A CORE CPU MANUAL EPSON 7 The difference between CALL and CALZ is shown in Figure 2.1.7.2.Bank 0 Bank 1 CALL without PSET can go anywhere in a page CALZ can only go to page 0 of the current bank CALL with PSET can go anywhere within a bank CALL and CALZ cannot go between banks Fig. 2.1.7.2 The difference between CALL and CALZ instructions 13 2.1.8 RET and RETS instructionsBank 0 Page 0 Program memory Bank 0 Page 10 Program memoryDDD.................... RET RETS 0AH DDD A,0 B,0 Fig. 2.1.8.1 Difference between RET and RETS instructions 2.1.9 Stack considerations for call instructions 14 2.2 Data Memory(within page) (page specification) 4-bit data Memory or I/O Register area Page 0 only 2.2.1 Data memory addressing 16 2.3 ALU (Arithmetic Logic Unit) and RegistersOperation Instruction ADD ADC SUB SBC AND OR XOR CP FAN RRC RLC NOT 2.3.1 D (decimal) flag and decimal operations 2.3.2 A and B registers 17 2.4 Timing Generator5-clock/7-clock instructions 12-clock instructions 2.4.1 HALT and SLP (sleep) modes 18 2.5 Interrupts2.5.1 Interrupt vectors 2.5.2 I (interrupt) flag 2.5.3 Operation during interrupt generation19 Fig. 2.5.3.1 Interrupt timing during executionS1C6200/6200A CORE CPU MANUAL EPSON 13 S1C6200 S1C6200A Fig. 2.5.3.2 Interrupt timing in the HALT modeSystem clock CPU clock Status Instruction S1C6200/6200A Fig. 2.5.3.3 Interrupt timing in SLEEP mode Fig. 2.5.3.4 Interrupt timing with PSETSystem clock CPU clock Status Instruction 20 S1C6200/6200A 21 2.5.4 Initial resetOn reset, the registers and flags are set as shown in Table 2.5.4.1. Table 2.5.4.1 Reset value 22 3I 3.1 Instruction Indices 32 3.2 Operands3.3 Flags1. Carry flag 2. Zero flag 3. Decimal flag 4. Interrupt flag 33 3.4 Instruction Types(I) (II) (III) (IV) (V) (VI) 3.5 Instruction Descriptions 34 ACPX MX,r ACPY MY,r 35 ADC r,i ADC r,q 36 ADC XH,i ADC XL,i 37 ADC YH,i ADC YL,i 38 ADD r,i ADD r,q 39 AND r,i AND r,q 40 CALL s CALZ s 41 CP r,i CP r,q 42 CP XH,i CP XL,i 43 CP YH,i CP YL,i 44 DEC MnDEC SP 45 DI EI 46 FAN r,i FAN r,q 47 INC Mn HALT Increment stack pointer by 1INC SP 48 INC X 49 INC Y JPBA 50 JP C,s JP NC,s 51 JP NZ,s JP s 52 JP Z,s LBPX MX,e 53 LD A,Mn LD B,Mn 54 LD Mn,A LD Mn,B 55 LDPX MX,i LDPX r,q 56 LDPY MY,i LDPY r,q 57 LD r,i LD r,q 58 LD r,SPH LD r,SPL 59 LD r,XH LD r,XL 60 LD r,XP LD r,YH 61 LD r,YL LD r,YP 62 LD SPH,r LD SPL,r 63 LD X,e LD XH,r 64 LD XL,r LD XP,r 65 LD Y,e LD YH,r 66 LD YL,r LD YP,r 67 NOP5 NOP7 68 NOT r OR r,i 69 OR r,q POP F 70 POP r POP XH 71 POP XL POP XP 72 POP YH POP YL 73 POP YP PSET p 74 PUSH F PUSH r 75 PUSH XH PUSH XL 76 PUSH XP PUSH YH 77 PUSH YL PUSH YP 78 RCF RDF 79 RET RETD eLoad immediate data e to memory, and increment X by 2, then return 80 RETS RLC r 81 RRC r RST F,i 82 RZF SBC r,i 83 SBC r,q SCF 84 SCPX MX,r SCPY MY,r 85 SDF SET F,i 86 SLP SUB r,q 87 SZF XOR r,i 88 XOR r,q 90 A1 Outline of DifferencesA2 Detailed Description of the DifferencesA2.1 Initial reset A2.2 InterruptOperation during interrupt issuanceAPPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU 91 b) At HALT modec) During "PSET" instruction execution Fig. A2.2.1 Timing chart of S1C6200A interrupt a) During instruction executionClock Status Instruction System clock CPU clock Status Instruction Clock Status Instruction 92 <Reference 1> Writing on the interrupt mask register during EI<Reference 2> Reading the interrupt factor flag during EI 94 LN O P 95 P RS X
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