Epson 6200A 1D

S1C6200/6200A CORE CPU MANUAL EPSON 1

1 DESCRIPTION

1DESCRIPTION

The S1C6200/6200A is the Core CPU of the S1C62 Family of CMOS 4-bit single-chip microcomput-

ers. The CPU features a highly-integrated architecture. Memory-mapped peripheral circuits can include

RAM, ROM, I/O ports, interrupt controllers, timers and LCD drivers, depending upon the application.

The memory address space is divided into program and data memory, each with data and address lines.

Program memory consists of on-chip ROM, containing instructions to be executed by the CPU. Data

memory consists of RAM and memory-mapped I/O, as determined by the design of the peripheral cir-

cuitry.

A large memory as well as instructions capable of 8-bit data manipulation enhance the functionality of the

S1C62 Family. Implementation of a common Core CPU ensures that a wide range of application-specific

devices can be designed and fabricated with the minimum turnaround time.

1.1 System Features

• Common Core CPU for all S1C62 Family microcomputers

• UP to 8,192 12-bit words of program memory (ROM)

• UP to 4,096 4-bit words of data memory (RAM/peripheral circuits)

• Memory-mapped I/O

• 5, 7 or 12 clock cycle instructions

• 109 instructions

• Up to 85 levels of subroutine nesting

• 8-bit stack pointer

• Up to 15 interrupt vectors

• Two standby modes

• Low-power CMOS process

1.2 Instruction Set Features

• Four addressing modes: one direct, two indirect, and one stack pointer

• Direct addressing transfers data to and from data memory with a single instruction, resulting in more

efficient code

• 8-bit load instructions and table look-up instructions

• Arithmetic operations in either hexadecimal or decimal

• Arithmetic and logical instructions: addition, subtraction, logical AND, OR, exclusive-OR, comparison

and rotation

1.3 Differences between S1C6200 and S1C6200A

There are some differences in the following operation/circuit between the S1C6200 and the S1C6200A.

For the detailes of each difference, refer to the section enclosed with parentheses.

• Initial setting of D (decimal) flag (refer to Section 2.5.5, "Initial reset".)

• Interrupt circuit

– Interrupt timing (refer to Section 2.5.3, "Operation during interrupt generation".)

– Writing to interrupt mask registers and reading of interrupt flags (refer to Appendix A, "S1C6200A

(Advanced S1C6200) Core CPU".)

Contents

Main NOTICE SEIKO EPSON CORPORATION 2001, All rights reserved. Configuration of product number Devices S1 C 60N01 F 0A01 Development tools S5U1 C 60R08 D1 1 00 Page S1C6200/6200A Core CPU Manual CONTENTS 1D 2M 3I B. INSTRUCTION INDEX ______________________________________ 87 Page 1D 1.1 System Features 1.2 Instruction Set Features 1.3 Differences between S1C6200 and S1C6200A 1 DESCRIPTION S1C6200 CORE CPU 8-bit address bus13-bit address bus Fig. 1.1 Block diagram 4-bit data bus S1C6200/6200A CORE CPU MANUAL EPSON 3 2M Fig. 2.1.1 Program memory configuration (within bank) PCB (between banks) 2.1 Program Memory (ROM) 2.1.1 Program counter block 2.1.2 Flags 2.1.3 Jump instructions 2.1.4 PSET with jump instructions 2.1.5 Call instructions 2.1.6 PSET instruction 2.1.7 CALZ instruction Fig. 2.1.7.1 The use of the CALZ instruction Bank 0 Page 0 EEE.................... RET 2.1.8 RET and RETS instructions Bank 0 Page 0 Program memory PSET CALL LD LD Bank 0 Page 10 Program memory DDD.................... RET RETS 2.2 Data Memory (within page) (page specification) 4-bit data Memory or I/O Register area Index register IY Stack pointer SP Register pointer RP 2.3 ALU (Arithmetic Logic Unit) and Registers Operation Instruction ADD ADC SUB SBC AND OR XOR CP FAN RRC RLC NOT 2.3.1 D (decimal) flag and decimal operations 2.3.2 A and B registers 2.4 Timing Generator 5-clock/7-clock instructions 12-clock instructions 2.4.1 HALT and SLP (sleep) modes 2.5 Interrupts 2.5.1 Interrupt vectors 2.5.2 I (interrupt) flag 2.5.3 Operation during interrupt generation Fig. 2.5.3.1 Interrupt timing during execution S1C6200/6200A CORE CPU MANUAL EPSON 13 S1C6200 S1C6200A Fig. 2.5.3.2 Interrupt timing in the HALT mode Fig. 2.5.3.3 Interrupt timing in SLEEP mode Fig. 2.5.3.4 Interrupt timing with PSET System clock CPU clock Status Instruction S1C6200/6200A S1C6200 2.5.4 Initial reset On reset, the registers and flags are set as shown in Table 2.5.4.1. Table 2.5.4.1 Reset value 3I 3.1 Instruction Indices a. Index by function b. Index in alphabetical order c. Index by operation code 3.1.1 By function Page Page 3.1.2 In alphabetical order Page Page 3.1.3 By operation code Page Page 3.2 Operands n n 3.3 Flags 1. Carry flag 3.4 Instruction Types (I) (II) (III) (IV) ACPX MX,r ACPY MY,r ADC r,i ADC r,q ADC XH,i ADC XL,i ADC YH,i ADC YL,i ADD r,i ADD r,q AND r,i AND r,q CALL s CALZ s CP r,i CP r,q CP XH,i CP XL,i CP YH,i CP YL,i DEC Mn DEC SP Decrement memory DI EI FAN r,i FAN r,q INC Mn HALT Increment stack pointer by 1INC SP INC X INC Y JPBA JP C,s JP NC,s JP NZ,s JP s JP Z,s LBPX MX,e LD A,Mn LD B,Mn LD Mn,A LD Mn,B LDPX MX,i LDPX r,q LDPY MY,i LDPY r,q LD r,i LD r,q LD r,SPH LD r,SPL LD r,XH LD r,XL LD r,XP LD r,YH LD r,YL LD r,YP LD SPH,r LD SPL,r LD X,e LD XH,r LD XL,r LD XP,r LD Y,e LD YH,r LD YL,r LD YP,r NOP5 NOP7 NOT r OR r,i OR r,q POP F POP r POP XH = XH POP XL = XL POP XP POP YH = YH POP YL POP YP = YP PSET p PUSH F PUSH r = r-register PUSH XH PUSH XL PUSH XP PUSH YH PUSH YL PUSH YP = YP RCF RDF RET RETD e Load immediate data e to memory, and increment X by 2, then return RETS RLC r RRC r r-register C RST F,i Cd r-register CC RZF SBC r,i SBC r,q SCF SCPX MX,r SCPY MY,r SDF SET F,i SLP SUB r,q SZF XOR r,i XOR r,q ABBREVIATIONS APPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU A1 Outline of Differences A2 Detailed Description of the Differences A2.1 Initial reset A2.2 Interrupt Operation during interrupt issuance b) At HALT mode c) During "PSET" instruction execution Fig. A2.2.1 Timing chart of S1C6200A interrupt a) During instruction execution Clock Status Instruction System clock CPU clock Status Instruction <Reference 1> Writing on the interrupt mask register during EI <Reference 2> Reading the interrupt factor flag during EI Page L N O P P R S X International Sales Operations AMERICA EUROPE ASIA