Intel IXD1110 manual CLK0 CLK1 CLK3, Gnd Gnd Gnd Gnd Gnd, GND CLK2

Page 37

Development Kit

Document Number: 250807

Revision Number: 003

Revision Date: June 27, 2003

 

 

5

 

 

4

 

 

3

 

 

2

 

 

1

 

 

Figure 16. Intel

Manual

D

C

2,10 uPx_Add[10:0]

2,9 uPx_RdN

2,9 uPx_WrN

2,9 uPx_CsN

2,9 uPx_RdyN

9,10 Bus_Busy

9,10 Bus_Request

9,10 Bus_Grant

9,10 CsN

9,10 GenP_CsN

9,10 RD/~WR

9,10 Start_XFER

9,10 TA

9,10 BUS_CLK

2,9,10 uPx_Data[31:0]

uPx_Add0

uPx_Add1

uPx_Add2

uPx_Add3

uPx_Add4

uPx_Add5

uPx_Add6

uPx_Add7

uPx_Add8

uPx_Add9

uPx_Add10

uPx_RdN

uPx_WrN

uPx_CsN

uPx_RdyN

Bus_Busy

Bus_Request

Bus_Grant

CsN

GenP_CsN

RD/~WR

Start_XFER

TA

BUS_CLK

uPx_Data0

uPx_Data1

uPx_Data2

uPx_Data3

uPx_Data4

uPx_Data5

uPx_Data6

uPx_Data7

uPx_Data8

uPx_Data9

uPx_Data10

uPx_Data11

uPx_Data12

uPx_Data13

uPx_Data14

uPx_Data15

uPx_Data16

uPx_Data17

uPx_Data18

uPx_Data19

uPx_Data20

uPx_Data21

uPx_Data22

uPx_Data23

uPx_Data24

uPx_Data25

uPx_Data26

uPx_Data28

uPx_Data27

uPx_Data29

uPx_Data30

uPx_Data31

2,10

HRESET

HRESET

POR

2,10

POR

2,10

IRQ

IRQ

 

2,9

TxPauseFR

TxPauseFR

 

TxPauseAdd0

 

2,9

TxPauseAdd0

TxPauseAdd1

 

2,9

TxPauseAdd1

TxPauseAdd2

 

2,9

TxPauseAdd2

TxPauseAdd3

 

2,9

TxPauseAdd3

D

C

® IXD1110 CPU Logic Probe Connectors

B

A

PROBE C: Address

PROBE A: Data Bus Bus & IXF1110

Signals

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

 

 

 

 

U19A

 

P6434 Probe

 

 

 

 

 

 

 

 

U20C

 

P6434 Probe

 

 

 

 

 

 

1

GND

 

 

GND

38

 

 

 

 

 

1

GND

 

 

GND

38

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

GND

 

 

GND

37

 

 

 

 

 

2

GND

 

 

GND

37

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BUS_CLK

3

CLK_0 CLK_1

36

 

 

 

 

 

3

CLK_3

 

 

Q1

36

 

 

 

 

 

 

 

 

 

 

 

IRQ

 

 

 

 

 

 

 

uPx_Data31

4

A3_7

 

 

A1_7

35

uPx_Data15

4

C3_7

 

 

C1_7

35

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

uPx_Data30

5

A3_6

 

 

A1_6

34

uPx_Data14

 

 

5

C3_6

 

 

C1_6

34

uPx_RdN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

uPx_Data29

6

A3_5

 

 

A1_5

33

uPx_Data13

 

 

6

C3_5

 

 

C1_5

33

uPx_WrN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

uPx_Data28

7

A3_4

 

 

A1_4

32

uPx_Data12

 

 

7

C3_4

 

 

C1_4

32

uPx_CsN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

uPx_Data27

8

A3_3

 

 

A1_3

31

uPx_Data11

 

 

8

C3_3

 

 

C1_3

31

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

uPx_Data26

9

A3_2

 

 

A1_2

30

uPx_Data10

uPx_Add10

9

C3_2

 

 

C1_2

30

uPx_RdyN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

uPx_Data25

10

A3_1

 

 

A1_1

29

uPx_Data9

uPx_Add9

10

C3_1

 

 

C1_1

29

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

uPx_Data24

11

A3_0

 

 

A1_0

28

uPx_Data8

uPx_Add8

11

C3_0

 

 

C1_0

28

Bus_Grant

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

uPx_Data23

12

A2_7

 

 

A0_7

27

uPx_Data7

uPx_Add7

12

C2_7

 

 

C0_7

27

Bus_Busy

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

uPx_Data22

13

A2_6

 

 

A0_6

26

uPx_Data6

uPx_Add6

13

C2_6

 

 

C0_6

26

Bus_Request

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

uPx_Data21

14

A2_5

 

 

A0_5

25

uPx_Data5

uPx_Add5

14

C2_5

 

 

C0_5

25

CsN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

uPx_Data20

15

A2_4

 

 

A0_4

24

uPx_Data4

uPx_Add4

15

C2_4

 

 

C0_4

24

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

uPx_Data19

16

A2_3

 

 

A0_3

23

uPx_Data3

uPx_Add3

16

C2_3

 

 

C0_3

23

GenP_CsN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

uPx_Data18

17

A2_2

 

 

A0_2

22

uPx_Data2

uPx_Add2

17

C2_2

 

 

C0_2

22

RD/~WR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

uPx_Data17

18

A2_1

 

 

A0_1

21

uPx_Data1

uPx_Add1

18

C2_1

 

 

C0_1

21

Start_XFER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

uPx_Data16

19

A2_0

 

 

A0_0

20

uPx_Data0

uPx_Add0

19

C2_0

 

 

C0_0

20

TA

 

 

 

 

GND GND GND GND GND

 

 

 

 

 

 

 

 

GND GND GND GND GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

39

40

41

42

43

 

 

 

 

 

 

 

 

 

39

40

41

42

43

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

PROBE D:

IXF1110 Pause

I/F Signals

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

 

 

 

U21D

 

P6434 Probe

 

 

 

 

 

 

1

GND

 

 

GND

38

 

 

 

 

 

 

 

 

 

 

 

 

 

2

GND

 

 

GND

37

 

 

 

 

 

 

 

 

 

 

 

 

 

3

Q0

 

 

 

CLK_2

36

 

 

TxPauseFR

 

 

 

 

 

 

HRESET

4

D3_7

 

 

D1_7

35

 

 

 

 

 

 

 

 

 

TxPauseAdd0

5

D3_6

 

 

D1_6

34

POR

 

 

 

 

 

 

 

 

 

TxPauseAdd1

6

D3_5

 

 

D1_5

33

 

 

 

 

 

 

 

 

 

 

 

TxPauseAdd2

7

D3_4

 

 

D1_4

32

 

 

 

 

 

 

 

 

 

 

 

TxPauseAdd3

8

D3_3

 

 

D1_3

31

 

 

 

 

 

 

 

 

 

 

 

 

 

9

D3_2

 

 

D1_2

30

 

 

 

 

 

 

 

 

 

 

 

 

 

10

D3_1

 

 

D1_1

29

 

 

 

 

 

 

 

 

 

 

 

 

 

11

D3_0

 

 

D1_0

28

 

 

 

 

 

 

 

 

 

 

 

 

 

12

D2_7

 

 

D0_7

27

 

 

 

 

 

 

 

 

 

 

 

 

 

13

D2_6

 

 

D0_6

26

 

 

 

 

 

 

 

 

 

 

 

 

 

14

D2_5

 

 

D0_5

25

 

 

 

 

 

 

 

 

 

 

 

 

 

15

D2_4

 

 

D0_4

24

 

 

 

 

 

 

 

 

 

 

 

 

 

16

D2_3

 

 

D0_3

23

 

 

 

 

 

 

 

 

 

 

 

 

 

17

D2_2

 

 

D0_2

22

 

 

 

 

 

 

 

 

 

 

 

 

 

18

D2_1

 

 

D0_1

21

 

 

 

 

 

 

 

 

 

 

 

 

 

19

D2_0

 

 

D0_0

20

 

 

 

 

 

GND GND GND GND GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

39

40

41

42

43

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

X = DO NOT INSTALL

B

Intel Communications Group

 

 

 

A

9750 Goethe Road

 

 

 

 

Sacramento, CA 95827

 

 

 

 

 

 

 

 

 

 

Title

 

 

 

 

 

 

IXD1110 - FX DEMO Board

 

 

 

 

 

 

 

 

Size

Document Number

 

 

Rev

 

B

CPU I/F Logic Probe Connectors

 

 

A1

 

 

 

 

 

 

Date:

Friday, May 24, 2002

Sheet 11 of

14

 

 

IXD1110 Demo Board

37

5

4

3

2

1

Image 37
Contents Development Kit Manual Intel IXD1110 Demo BoardDevelopment Kit Manual Contents Tables FiguresRevision History Contents About This Kit IntroductionAdditional Equipment Required About The IXD1110 Demo Board FeaturesComponent Description Intel IXD1110 Demo Board Principal ComponentsFpga Quick Start SetupTypical Test Setup Typical Test SetupIntel IXF1110 CPU Daughter Card CPU Daughter CardIXF1110 Register Modifications on Startup CPU FpgaPC Requirements IXF1110 SoftwareChanging the IP Address of the CPU Daughter Card Optional Installing the IXF1110 SoftwareDram OK Reset Jumper JP2 Optional ConfigurationsJtag Test Signals Jtag Test Signals JP1IXF1110 LED Behavior LEDsTest Points Reset Test PointsIXF1110 Input Clock Test Points Gbic Test PointsMictor Connector Test Points Sheet 1 Mictor ConnectorsGbic Test Points Sheet 2 Mictor Connector Test Points Sheet 2 Power and Ground Test PointsPower Test Points Sheet 1 Test Point Symbol DescriptionGround Test Points Power Test Points Sheet 2Unused Test Points Unused Test PointsTest Points Description IXD1110 Demo Board Power Revision A1 SchematicsDigital Power 2.5 Digital Power1.8GND Analog Power Intel IXD1110 Analog PowerControl I2C Data MODDEF3 MODDEF0 I2CDATA3I2CDATA4IXF0 I2CDATA4AC9 AB9I2CDATA6 MODDEF6SerDes/GBIC Port IXD1110MODDEF9 L1 I2CDATA9IXF0SPI-4 Phase 2 TX SPI-4 Phase 2 RXIXD1110 SPI4-2 Srclk SERSrclr RclkIXF1110 & CPU Interfaces Power+2.5V +3.3VConnectors GND GND GND GND GND CLK0 CLK1 CLK3GND CLK2 Intel IXD1110 Demo Board Bill of Materials Rev. A1 Bill of MaterialsReference Designator Description Manufacturer Part Number Misc Bottom Testpoint

IXD1110 specifications

The Intel IXD1110 is an advanced integrated circuit that serves as a highly efficient and versatile solution for various communication and data processing applications. Built on Intel's cutting-edge technology, the IXD1110 showcases enhanced performance characteristics tailored for modern industrial and embedded systems.

One of the most notable features of the IXD1110 is its robust processing capability. Designed to support high-speed data transfer, this device operates with a clock frequency of up to 500 MHz. Such a high processing speed ensures that the IXD1110 can handle data-heavy applications with ease, making it an ideal choice for real-time data processing tasks.

In terms of connectivity, the IXD1110 boasts multiple communication interfaces. It supports Ethernet, SPI, and I2C protocols, allowing seamless integration into various system architectures. The Ethernet interface ensures high-bandwidth connectivity, giving developers the flexibility to connect the IXD1110 to both wired and wireless networks. This opens up possibilities for IoT (Internet of Things) applications, where reliable and fast communication is critical.

Another standout feature of the IXD1110 is its low-power consumption, which is a significant consideration for embedded systems and battery-powered devices. Intel has implemented advanced power management technologies in the IXD1110, enabling it to operate efficiently while minimizing energy usage. This characteristic not only extends the lifespan of the devices it powers but also reduces overall operational costs.

The IXD1110 also includes advanced security features, catering to the growing demand for secure processing in connected devices. Integrated hardware security mechanisms help safeguard against vulnerabilities and attacks, ensuring data integrity and protecting sensitive information.

Additionally, the IXD1110 is designed for scalability, allowing developers to adapt the device to a wide range of applications, from automotive systems to industrial automation. Its flexible architecture accommodates future upgrades and enhancements, making it a long-term investment for companies looking to future-proof their systems.

In conclusion, the Intel IXD1110 stands out with its high processing speeds, versatile connectivity options, low power consumption, advanced security features, and scalability. These attributes make it a compelling choice for organizations looking to leverage cutting-edge technology in their communication and data processing systems. As industries continue to evolve towards greater connectivity and automation, the IXD1110 is positioned as a key enabler in this technological transformation.