BIOS SETUP
Advanced Chipset Features
This Setup menu controls the configuration of the chipset.
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
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| DRAM Timing Selectable | By SPD | ITEM HELP |
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| CAS Latency Time | 2 | Menu Level > |
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| Active to Precharge Delay | 6 |
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| DRAM RAS# to CAS# Delay | 3 |
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| DRAM RAS# Precharge | 3 |
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| DRAM Data Integrity Mode | ECC |
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| MGM Core Frequency | Auto Max 266MHz |
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| System BIOS Cacheable | Enabled |
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| Video BIOS Cacheable | Enabled |
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| Memory Hole at | Disabled |
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| Delayed Transaction | Enabled |
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| Delay Prior to Thermal | 16 Min |
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| AGP Aperture Size (MB) | 64 |
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| Enabled |
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| 32MB |
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| Boot Display | CRT+LVDS |
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| Panel Scaling | Auto |
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| Panel Number | 1024x768耟18bit SC |
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DRAM Timing Selectable
This option refers to the method by which the DRAM timing is selected. The default is By SPD.
CAS Latency Time
You can configure CAS latency time in HCLKs as 2 or 2.5 or 3. The system board designer should set the values in this field, depending on the DRAM installed. Do not change the values in this field unless you change specifications of the installed DRAM or the installed CPU.
Active to Precharge Delay
The default setting for the Active to Precharge Delay is 7.
DRAM RAS# to CAS# Delay
This option allows you to insert a delay between the RAS (Row Address Strobe) and CAS (Column Address Strobe) signals. This delay occurs when the SDRAM is written to, read from or refreshed. Reducing the delay improves the performance of the SDRAM.
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