ATC6430M Mainboard

Chapter 3 Award BIOS Setup

SDRAM CAS Latency Time When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM timing. The choices: 2,3. “2” gives faster performance and “3” gives more stable performance.

SDRAM Cycle Time Tras/Trc Select the number of SCLKs for an access cycle. “5/7” gives faster performance and “6/8” gives more stable performance.

SDRAM RAS-to-CAS Delay This field lets you insert a timing delay between the CAS and RAS strobe signals, used when DRAM is written to, read from, or refreshed. “2” gives faster performance and “3” gives more stable performance. This field applies only when synchronous DRAM is installed in the system.

SDRAM RAS Prechage Time If an insufficient number of cycles is allowed for the RAS to accumulate its charge before DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain data. This field applies only when synchronous DRAM is installed in the system.

System BIOS Cacheable Selecting Enabled allows the caching of the system BIOS ROM area, resulting in better system performance. However, if any program writes to this memory area, a system error may result.

Video BIOS Cacheable Selecting Enabled allows the caching of the video BIOS ROM area, resulting in better system performance. However, if any program writes to this memory area, a system error may result.

Memory Hole At 15M-16M Certain space in memory can be reserved for ICH/ICH0.

Delay Transaction This chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support compliance with PCI specification version 2.1. The choice : Enabled, disabled space

On-chip Video Window Size Determine the size of memory space that can be allocated for on-chip graphics device.

The following items are optional for onboard display cache setting:

CAS# Latency The number of clock cycles of CAS latency depends on the Display Cache timing. The choices: 2,3. “2” gives faster performance and “3” gives more stable performance.

Paging Mode Control Close: the GMCH will precharge all during the service of a