SDRAM RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast gives faster performance; slow gives more stable performance. This field applies only when synchronous
DRAM is installed in the system.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h- FFFFFh, resulting in better system performance. However, if any program writes to this memory area, a system error may result. The choices:
Enabled, Disabled
Video BIOS Cacheable
Selecting Enabled allows caching of the video BIOS ROM at C0000h to C7FFFh, resulting in better video performance. However, if any program writes to this memory area, a system error may result. The choices:
Enabled, Disabled Memory
Hole At 15-16m
In order to improve performance, certain space in memory is reserved for ISA cards. This memory must be mapped into the memory. The choices:
CPU Latency Timer
During enable, a deferrable CPU cycle will only be Deferred after it has been in Snoop Stall for 31 clocks and another ADS# has arrived. During disable, a deferrable CPU cycle will be deferred immediately after the
GMCH receives another ADS#.
Delayed Transaction
The chipset has an embedded