Intel PCI-471LF M2 Dram Data Integrity Mode, System Bios Cacheable, Video Bios Cacheable

Chapter 4 Award BIOS Setup

DRAM DATA INTEGRITY MODE:

Select Parity or ECC (error-correcting code), according to the type of installed DRAM.

SYSTEM BIOS CACHEABLE:

Selecting Enabled allows caching of the system BIOS ROM at F0000h- FFFFFh, resulting in better system performance. However, if any program writes to this memory area, a system error may result.

VIDEO BIOS CACHEABLE:

Select Enabled allows caching of the video BIOS, resulting in better system performance. However, if any program writes to this memory area, a system error may result.

MEMORY HOLE AT 15M-16M:

You can reserve this area of system memory for ISA adapter ROM. When this area is reserved, it cannot be cached. The user information of peripherals that need to use this area of system memory usually discusses their memory requirements.

DELAYED TRANSACTION:

The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support compliance with PCI specification version 2.1.

AGP APERTURE SIZE:

This field determines the effective size of the Graphic Aperture used for a particular GMCH configuration. It can be updated by the GMCH-specific BIOS configuration sequence before the PCI standard bus enumeration sequence takes place. If it is not updated then a default value will select an aperture of maximum size.

PCI-471LF USER′S MANUAL Page: 4-11