EM78M611E
Universal Serial Bus Series Microcontroller
8.2.2.5R4 (RAM Select Register) Default Value: (0B_00XX_XXXX)
Bit 7 |
| Bit 6 |
| Bit 5 |
| Bit 4 |
| Bit 3 |
| Bit 2 |
| Bit 1 |
| Bit 0 |
BK1 |
| BK0 |
| Ad5 |
| Ad4 |
| Ad3 |
| Ad2 |
| Ad1 |
| Ad0 |
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R4 (RAM select register) contains the address of the registers.
R4 [0~5] used to select registers in 0x00h~0x3Fh. The address 0x00~0x1F is common space. After 0x1Fh, SRAM is divided into four banks, using Bank Select Register.
R4 [6, 7] used to select the registers bank (refer to the table below). The following are two examples:
(1)R4=00001100 and R4=10001100 point to the same register 0x0Ch. Since 0x0Ch is in the common space, Bit 6 and Bit 7 are meaningless.
(2)R4=10111100 points to the register 0x3C in Bank 2.
R4[7]Bk1 | R4[6]Bk0 | RAM Bank # |
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0
1
1
0
1
0
1
Bank 0
Bank 1
Bank 2
Bank 3
8.2.2.6 | R5 (Port 5 I/O Register) | Default Value: (0B_0000_0000) |
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Bit 7 |
| Bit 6 | Bit 5 |
| Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
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P57 |
| P56 | P55 |
| P54 | P53 | P52 | P51 | P50 |
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8.2.2.7 | R6 (Port 6 I/O Register) | Default Value: (0B_0000_0000) |
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Bit 7 |
| Bit 6 | Bit 5 |
| Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
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P67
P66
P65
P64
P63
P62
P61
P60
8.2.2.8 |
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| R7 | (Port 7 I/O Register) | Default Value: (0B_0000_X000) |
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| Bit 7 |
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| Bit 6 |
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| Bit 5 |
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| Bit 4 |
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| Bit 3 |
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| Bit 2 |
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| Bit 1 |
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| Bit 0 |
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| P77 |
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| P76 |
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| D+ / P74 / CLK |
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| P72 |
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| P71 |
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| P70 |
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8.2.2.9 |
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| R8 | (Port 8 I/O Register) | Default Value: (0B_0000_0000) |
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| Bit 7 |
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| Bit 6 |
| Bit 5 |
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| Bit 4 |
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| Bit 3 |
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| Bit 2 |
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| Bit 1 |
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| Bit 0 |
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| P87 |
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| P86 |
| P85 |
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| P84 |
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| P83 |
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| P82 |
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| P81 |
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| P80 |
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8.2.2.10 | R9 | (Port 9 I/O Register) Default Value: (0B_X00X_0000) |
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| Bit 7 |
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| Bit 6 |
| Bit 5 |
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| Bit 4 |
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| Bit 3 |
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| Bit 2 |
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| Bit 1 |
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| Bit 0 |
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| − |
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| P96 |
| P95 |
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| P93 |
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| P92 |
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| P91 |
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| P90 |
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Product Specification (V1.11) 04.20.2007 |
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| • 13 | |||||||||||||||||
(This specification is subject to change without further notice)