Fujitsu MB39A104 manual Timer-latch short-circuit protection circuit

MB39A104

2. Setting Time Constant for Timer-Latch Short-Circuit Protection Circuit

Each channel uses the short-circuit detection comparator (SCP Comp.) to always compare the error amplifier′s output level to the reference voltage (3.1 V Typ).

While DC/DC converter load conditions are stable on all channels, the short-circuit detection comparator output remains at “L” level, and the CSCP terminal (pin 8) is held at “L” level.

If the load condition on a channel changes rapidly due to a short-circuit of the load, causing the output voltage to drop, the output of the short-circuit detection comparator goes to “H” level. This causes the external short- circuit protection capacitor CSCP connected to the CSCP terminal to be charged at 1 ∝A.

Short-circuit detection time (tSCP) tSCP (s) =: 0.73 ⋅ CSCP (∝F)

When the capacitor CSCP is charged to the threshold voltage (VTH =: 0.73 V), the latch is set and the external FET is turned off (dead time is set to 100%). At this time, the latch input is closed and the CSCP terminal is held at “L” level. If a short-circuit is detected on either of the two channels, both channels are shut off.

When the power supply is turned on back or VREF terminal (pin 17) voltage is less than 2.4 V (Min) by setting CTL terminal (pin 24) to “L” level, the latch is released.

•Timer-latch short-circuit protection circuit

	(FB2)
VO	16
	FB1 9
R1	(−INE2) 15		Error
		−
	10		Amp
	−INE1
R2		+
		(1.24 V)
					SCP	+
					Comp.
						+
						−
						(3.1 V)
		(1 ∝A)
	CSCP
	8					VREF
			S	R
			Latch			UVLO

To each channel Drive

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