Apple PowerPC G5 manual Highly Parallel Execution Core, Aggressive Queuing and Register Renaming

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Up to 215 in-flight instructions

A wide architecture with 12 discrete processing units enables the PowerPC G5 to contain up to 215 in-flight instructions simultaneously— 71 percent more than the 126 instructions in a Pentium 4.

White Paper

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PowerPC G5

PowerPC G5 Architecture

Highly Parallel Execution Core

At the heart of the PowerPC G5 is an entirely new superscalar, superpipelined execution core, composed of 12 functional units that execute different types of instructions con- currently for massive data throughput. Before instructions are dispatched into the functional units, they are arranged into groups of up to five. Within the core alone, the PowerPC G5 can track up to 20 groups at a time, or 100 individual instructions. This efficient group-tracking scheme enables the PowerPC G5 to manage an unusually large number of instructions “in flight”: 20 instructions in each of the five dispatch groups, in addition to 100-plus instructions in the various fetch, decode, and queue stages.

Aggressive Queuing and Register Renaming

The PowerPC G5 includes extensive instruction queueing and renamable data registers that maximize the utilization of each functional unit. Once an instruction group is dis- patched into the execution core, it is broken into individual instructions, which proceed to the appropriate functional unit. Each functional unit has its own dedicated queue, where multiple instructions are sequenced for processing.

At the same time, the load/store units load the associated data from L1 cache into the data registers behind the units that will be processing the data. To improve processing efficiency, the PowerPC G5 features a large number of rename registers that act as proxies, or placeholders, until the appropriate data arrives for execution. The instruction is held in queue, allowing other operations to take place until the actual data is loaded into the registers.

When operations on the data are complete, the PowerPC G5 recombines the instructions into the original groups of five, and the load/store units store the data in cache or main memory to complete processing.

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Contents PowerPC G5 White Paper JulyContents Key Features IntroductionAn Exponential Leap in Computing Power Memory Addressing up to 18 ExabytesHigh-Precision Calculations in a Single Clock Cycle Clock Speeds up to 2GHzIndustry-Leading 1GHz Frontside Bus Full Support for Symmetric MultiprocessingNative Compatibility with 32-Bit Application Code Next-Generation PowerPC Architecture Ultrafast Access to Data and InstructionsHighly Parallel Execution Core Aggressive Queuing and Register RenamingOptimized 128-Bit Velocity Engine Two Double-Precision Floating-Point UnitsTwo Integer Units Two Load/Store UnitsState-of-the-Art Process Technology from IBM Condition RegisterThree-Component Branch Prediction Logic Industry-Leading Performance Spec CPU2000Spec CPU2000 Single-Processor Speed Spec CPU2000 Dual Processor System Throughput Technical Specifications Bit PowerPC processor architectureFrontside bus Wide execution corePhysical specifications Comparison of PowerPC G4 and PowerPC G5For More Information Three-component branch prediction logic
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