Sun Microsystems X4200 M2 manual Enabling Technology, Next-Generation AMD Opteron Processor Basics

Enabling Technology

Next-Generation AMD Opteron Processor Basics

The Next-Generation AMD Opteron processor leverages the same proven Direct Connect Architecture and CMP (Chip-level Multi-Processing) design features of the Single- and Dual-Core AMD Opteron (formerly known as Rev E) processors, including:

•64-bit operating systems to provide full, transparent, and simultaneous 32-bit and 64-bit platform application multitasking

•Direct Connect Architecture

•Addresses and helps reduce the real challenges and bottlenecks of system architecture

•Memory is directly connected to the CPU, optimizing memory performance

•I/O is directly connected to the CPU, for more balanced throughput and I/O

•CPUS are connected directly to CPUS allowing for more linear symmetrical multiprocessing

•Integrated DDR2 Memory Controller

•A 128-bit wide, on-chip DDR2 memory controller that supports ECC and ChipKill technologies and provides low-latency memory bandwidth which scales as processors are added

•AMD HyperTransportTM Technology

•Provides a scalable bandwidth interconnect between processors, I/O subsystems and other chipsets

•Dedicated 1MB L2 Cache for each core

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•10.7 GB/s @

•DDR2-667

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72bit	72bit	Link1	Link2	Link3	24 GB/s @
					1000MHz
DDR2 Integrated		HyperTransport™			HyperTransport
Memory Controller		Technology
	Crossbar
System Request Interface
AMD64 Core 1		AMD64 Core 2
PowerNow!™		PowerNow!™
AMD Virtualization		AMD Virtualization
	1MB		1MB
L2 Cache			L2 Cache

Figure 1: Next-Generation AMD Opteron Processor Design for Socket F (1207)

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