Compaq Mega-Post manual Acer, Error Code 0A

Page 6
AMI
AST Award

Appendix A

 

Error Code - 06

 

(06)ROM is enabled. Calculating ROM BIOS checksum, and waiting for Keyboard

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controller input buffer to be free. Calculating ROM BIOS checksum.. Video disabled and sys-

tem timer test begin Video disabled and system timer counting

 

 

OK.

AST

(06)Support chipset initialize.

Award

(06)Test memory refresh toggle; RAM must be periodically refreshed in-order to

keep the memory from decaying. This function assures that the memory refresh

 

function is working properly. Initialize chips.

Chips & Tech (06)64K RAM Failed.

Phoenix&Dell (06)Initialize system hardware (Beep)=1-1-2-3.DMA page register write/read test

 

in-progress or fail.

 

Error Code - 07

AMI

(07)ROM BIOS checksum passed. CMOS shutdown register test to be done

 

next.ROM BIOS checksum passed, Keyboard controller I/B free. Going to issue the

 

BAT command to keyboard controller. Going to issue the BAT command to keyboard

Award

controller.CH-2 of 8254 initialization half way.CH-2 of 8253 test OK

(07)Verifies CMOS's basis R/W functionality Test CMOS interface and battery

 

status; Verifies CMOS is working correctly, detects bad battery. Setup low memory;

 

Early chip set initialization; Memory presence test; OEM chip set routines; Clear

 

low 64K of memory; Test first 64K memory; clear lower 256K of memory, enable

 

parity checking and test parity in lower 256K; test lower 25 If the BIOS detects

 

error 2C,2E,or 30(base 512K RAM error),it displays 6K memory. Set up stack,beep.

 

Read/write/verify CPU registers.

Chips & Tech (07)64K RAM failed data test (Base Memory)

 

Error Code - 08

ACER

(08)Shutdown 0.

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(08)CMOS shutdown register test done. CMOS checksum calculation to be done

 

next. BAT command to keyboard controller is issued. Going to verify the BAT command.

 

Going to verify the BAT command. CH-2 of timer initialization over.

Award

CH-2 delta count test OK

(08)Setup low memory; Early chip set initialization; Memory presence test; OEM

 

chip set routines; Clear low 64K of memory; Test first 64K memory; clear lower

 

256K of memory, enable parity checking and test parity in lower 256K; test lower

 

256K memory. Set up stack, beep. Setup interrupt vector table in lower 1K RAM

 

area; Initialize first 120 interrupt vectors with SPURIOUS_INT_HDLR and initialize INT 00h-

 

1Fh according to INT_TBL. Initialize CMOS timer.

Chips & Tech (08)Interrupt Controller bad.

Phoenix&Dell (08)Initialize chipset registers with POST values. [Beep]= 1-3-1 RAM refresh verification in-progress or failure.

Error Code - 09

(09)CMOS checksum calculation is done, CMOS diag byte written. CMOS initialize to begin. Keyboard controller BAT result verified. Keyboard command

byte to be written next.(09)Keyboard command byte to be written next. CH-1 of timer initialization over. CH-1 delta count test OK.

(09)Verify BIOS ROM checksum, flush external cache.

(09)Program the configuration register of Cyrix CPU. OEM specific cache initialization., Early Cache initialization; Cyrix CPU initialization; cache initialization. Test CMOS RAM checksum; beep; also test extended storage of parameters in the motherboard chipset; if not warm- booting; display the Test

CMOS RAM checksum message, if bad, or insert key pressed, load defaults if bad. Check BIOS Checksum.

Chips & Tech (09)Unexpected interrupt is occurring.

Phoenix&Dell (09)Set POST flay.(Beep)=1-1-3-2. 1st 64K RAM test in-progress.

 

Error Code - 0A

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(0A)CMOS initialization done(if any). Keyboard command byte code is issued.

 

Going to write command byte data. Go- ing to write command byte data. CH-0 of

Award

timer initialization over. CH-0 delta count test OK

(0A)Initialize the first 32 interrupt vectors. Initialize INTs 33 to 120.Early Power Management

 

initialization. Setup interrupt vector table in lower 1K RAM area; Initialize first 120 interrupt

 

vectors with SPURIOUS_INT_HDLR and initialize

 

INT 00h-1Fh according to INT_TBL. Initialize key- board; Detect type of keyboard

 

controller(optional 8242 or 8248, with Nedadon XOR gate control); Set NUM_LOCK status.

Reset keyboard test keyboard controller interface to verify it

returned AAH and responded to enable/disable commands, set keyboard buffer, enable keyboard and keyboard interrupts for normal use, beep, halt .Initialize Video controller.

Chips & Tech (0A)Timer cannot interrupt.

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Contents Mega-Post PCI-Diagnostic Card Users GuideSystem Requirements Mega-Post PCI-Diagnostic Card IndicatorsTrademarks Tech SupportUsers Guide Power On Self-Test Post Codes PCI Signal DefinitionTroubleshooting During Post Users Guide Post CodesError Code Error Code-00Error Code-01 Appendix aError Code 0A AcerError Code 0D Error Code 0BError Code 0C Error Code 0EDMA Error Code 1D Error Code 1BError Code 1C Error Code 1EError Code 1F Error Code 2D Error Code 2AError Code 2C Error Code 2E38CMOS RAM Error Code 3D Error Code 3BError Code 3C Error Code 3EError Code 4C Error Code 4AError Code 4B Error Code 4D50Protected mode Error Code 5C Error Code 5AError Code 5B Error Code 5DError Code 6C Error Code 6AError Code 6B Error Code 6EError Code 7C Error Code 7AError Code 7B Error Code 7DError Code 8C Error Code 8AError Code 8B Error Code 8DError Code 9A Error Code 9CError Code 9E Error Code A1 Error Code 9FError Code A0 Error Code A2Error Code be Error Code B6Error Code B7-BD Error Code C0Error Code E1,E2 Error Code CD-CFError Code D0-DC Error Code E3