|
| (' |
| ||||
|
| ||||||
| The BIOS also issues Port 80h codes that can be displayed using a suitable diagnostic card. The | ||||||
| codescan be used to determine the failure. |
|
| ||||
|
|
|
|
|
|
| |
|
|
|
|
|
|
| |
| 02h |
|
| Verify Real Mode |
|
| |
|
|
|
|
|
| ||
| 03h |
|
| Disable |
| ||
|
|
|
|
|
|
|
|
| 04h |
|
| Get CPU type |
|
|
|
|
|
|
|
|
|
| |
| 06h |
|
| Initialise system hardware |
|
| |
|
|
|
|
|
| ||
| 08h |
|
| Initialise chipset with initial POST values |
| ||
|
|
|
|
|
|
| |
| 09h |
|
| Set IN POST flag |
|
| |
|
|
|
|
|
|
| |
| 0Ah |
|
| Initialise CPU registers |
|
| |
|
|
|
|
|
|
| |
| 0Bh |
|
| Enable CPU cache |
|
| |
|
|
|
|
|
| ||
| 0Ch |
|
| Initialise caches to initial POST values |
| ||
|
|
|
|
|
|
| |
| 0Eh |
|
| Initialise I/ O component |
|
| |
|
|
|
|
|
|
| |
| 0Fh |
|
| Initialise the local bus IDE |
|
| |
|
|
|
|
|
| ||
| 10h |
|
| Initialise Power Management |
| ||
|
|
|
|
|
| ||
| 11h |
|
| Load alternate registers with initial POST values |
| ||
|
|
|
|
|
| ||
| 12h |
|
| Restore CPU control word during warm boot |
| ||
|
|
|
|
|
| ||
| 13h |
|
| Initialise PCI Bus Mastering devices |
| ||
|
|
|
|
|
| ||
| 14h |
|
| Initialise keyboard controller |
| ||
|
|
|
|
|
|
| |
| 16h |
|
| BIOS ROM checksum |
|
| |
|
|
|
|
|
| ||
| 17h |
|
| Initialise cache before memory autosize |
| ||
|
|
|
|
|
|
| |
| 18h |
|
| 8254 timer initialisation |
|
| |
|
|
|
|
|
| ||
| 1Ah |
|
| 8237 DMA controller initialisation |
| ||
|
|
|
|
|
| ||
| 1Ch |
|
| Reset Programmable Interrupt Controller |
| ||
|
|
|
|
|
|
| |
| 20h |
|
| Test DRAM refresh |
|
| |
|
|
|
|
|
| ||
| 22h |
|
| Test 8742 Keyboard Controller |
| ||
|
|
|
|
|
| ||
| 24h |
|
| Set ES segment register to 4 GB |
| ||
|
|
|
|
|
|
| |
| 26h |
|
| Enable A20 line |
|
| |
|
|
|
|
|
|
| |
| 28h |
|
| Autosize DRAM |
|
| |
|
|
|
|
|
| ||
| 29h |
|
| Initialise POST Memory Manager |
| ||
|
|
|
|
|
|
| |
| 2Ah |
|
| Clear 512 KB base RAM |
|
| |
|
|
|
|
|
| ||
| 2Ch |
|
| RAM failure on address line |
| ||
|
|
|
|
|
| ||
| 2Eh |
|
| RAM failure on data bits of low byte of memory bus |
| ||
|
|
|
|
|
| ||
| 2Fh |
|
| Enable cache before system BIOS shadow |
| ||
|
|
|
|
|
| ||
| 30h |
|
| RAM failure on data bits of high byte of memory bus |
| ||
|
|
|
|
|
| ||
| 32h |
|
| Test CPU bus- clock frequency |
| ||
|
|
|
|
|
| ||
| 33h |
|
| Initialise Phoenix Dispatch Manager |
| ||
|
|
|
|
|
|
| |
| 34h |
|
| Test CMOS RAM |
|
| |
|
|
|
|
|
| ||
| 35h |
|
| Initialise alternate chipset registers. |
| ||
|
|
|
|
|
|
|
|
MITSUBISHI ELECTRIC MOTHERBOARD DIVISION | PAGE 30 OF 45 |