Fairchild AN-7511 manual VCO Timing Logic

Application Note 7511

It’s impractical, however, to rate an inverter based on locked- rotor current. You can avoid this necessity by adjusting the switching regulator’s output voltage and by providing a fixed output-current limit slightly higher than the maximum full- load current. This way, the current requirements during start- up will never exceed the current capability of an efficiently sized inverter.

For example, consider a 2-hp, 3-phase induction motor spec- ifying VL at 230V RMS and full-load current (ILFL) at 6.2A

RMS. For the peak current of 8.766A, you can select IGT type D94FR4. This device has a reverse-breakdown SOA (RBSOA) of 10A, 500V for a clamped inductive load at a junction temperature of 150oC. A 400V IGT could also do the job, but the 500V choice gives an additional derating safety margin. You must set the current limit at 9A to limit the in- rush current during start-up. Note that thanks to the IGT’s adequate RBSOA, you don’t need turn-off snubbers.

	2.		5V
	3.3k
	7 4		8 3
2.7k	NE555
	6 2		1 5
1000pF
	VCO &	A	4.7k
	TIMING
	LOGIC

						24V					DC BUS
					470		PIEZOCOUPLER
									1N914 E		Q1
					D
											D94FR4
1N914	1k		C	1k
								PZT61343			4.7k
						Q8			1N914
					24V	2N3903
0.001∝F	1N914	4.7k		Q8
											φA
				2N3903	470
5V
470					D33030
					Q3	3			1N914	F	Q
B											2
					22∝F						D94FR4
Q7							10
		470
									2N3903		4.7k
					C1
2N3903									Q5
				D29E10				10
					Q4
						1N914

FIGURE 11A. PROVIDING PROPERLY TIMED DRIVE TO THE IGTS, THE CIRCUIT USES PIEZO COUPLING TO THE UPPER POWER DEVICE. THE 3-TRANSISTOR DELAY CIRCUIT PROVIDES THE NEEDED 15o LAG TO THE LOWER IGT TO AVOID CROSS CONDUCTION.

	VOLTS
24V
F
24V
E	TIME
24V
D	TIME
5V
C	TIME
	100kHz
5V
B	TIME
5V
A	TIME

FIGURE 11B. THE TIMING DIAGRAM SHOWS THE 555’S 108-KHz DRIVE TO THE PIEZO DEVICE AND THE LATTER’S SLOW RESPONSE.

©2002 Fairchild Semiconductor Corporation Application Note 7511 Rev. A1