Vcxo Inputs and Outputs J16−J18 | Texas Instruments CDCM7005

Hardware Configuration

When the CDCM7005 is powered up, it defaults to five LVPECL outputs. However, this EVM is configured as follows:

-Y0 − Y2 = LVPECL

-Y3, Y4 = LVCMOS (in addition Y4 has an option for a custom filter)

The reference input clock signal has to be applied to J1 or J6. The reference input clock signal can be sensed on J4. In this case, close the bridge J5 (the oscilloscope’s 50 Ω may be used to terminate the 50-Ω trace). The reference input clock sense line is matched to the LVPECL outputs line to avoid any additional delay offset. The input is ac-coupled (C4).

3.2.6VC(X)O Inputs and Outputs (J16−J18)

The CDCM7005 requires an external VC(X)O in order to complete the PLL loop. The VC(X)O adjusts the frequency and phase depending on the control voltage level coming from the loop filter and provide the input clock to the LVPECL block.

Another option would be to use an external source via J16 and J18.

3.2.7AC-Coupling at PRI_REF (C1, R4, R6) and SEC_REF (C5, R13, R15)

An ac-coupling is provided at PRI_REF and SEC_REF to ease the use of the CDCM7005 with different signaling levels (LVCMOS, LVPECL, LVDS,...). However, the ac-coupling will increase the PLL stabilization time after power up due to transient effects. It also increases the switching time between PRI_REF and SEC_REF in case of automatic reference clock switching. Therefore, the ac-coupling must be removed for optimized system performance (C1 and C5 has to be replaced with an 0-Ω resistor and R4, R6, R13, and R15 have to be removed).

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