T-SGPIO 0/1 & 3-SGPIO 0/1 Headers
Two
Pin Definitions
Purpose Input/Output) headers are located next to the
3 on the |
Pin# |
| Definition |
1 |
| NC |
| ||
3 |
| Ground |
| ||
|
|
|
5Load
7Clock
Pin Definition
2 NC
4 DATA Out
6Ground
8NC
headers are used to communicate with |
the enclosure management chip in the |
system. See the table on the right for |
pin definitions. Refer to the board layout |
below for the locations of the headers. |
Alarm Reset
If three power supplies are installed and Alarm Reset (JP5) is enabled, the system will notify you when any of the three power modules fail. Connect JP5 to a
NC: No Connections
Alarm Reset | ||
Pin Definitions | ||
|
| |
Pin Setting | Definition | |
|
| |
Pin 1 |
| Ground |
|
|
|
Pin 2 |
| +5V |
|
|
|
| KB/MOUSE |
USB 0/1 | IPMI LAN |
COM1 |
|
JPUSB1 JPW2 | SMBUS_PS1 | JPW1 | FAN1 |
| DIMM3A |
|
|
| DIMM3B |
| CPU FAN |
|
|
| |
| DIMM2A |
|
|
| DIMM2B |
|
|
LAN CTRL | DIMM1A |
|
|
for IPMIl LAN |
|
|
DIMM1B
A.T-SPGIO 0
B.
VGA | LAN |
CTRL1 | |
| LAN1 |
| LAN2 |
| LAN |
| CTRL2 |
| FAN5 |
Intel Processor
Slot6
Intel
North Bridge
Battery
SPKR1
JBT1
JWOL
|
| JLED |
| |
|
| LE1 |
| |
|
|
| JF1 |
|
|
|
|
| 1 |
|
| JOH |
| |
| JWD |
| ||
FAN2 |
|
| ||
A |
| JD1 | ||
| JAR | E | ||
|
| |||
|
| |||
|
|
| B |
D.3-SPGIO 1 (X8ST3-F only)
E.Alarm Reset
SI/O | |
| COM2 |
| 1 |
Slot5
Slot4 | BMC |
Firmware |
JPL1 |
|
|
|
JPL2 |
| JPG1 |
|
Slot3 |
|
| |
|
| BMC CTRL | |
Slot2 PCI 33MHz |
| WPCM 450 | |
| JBMC1 |
| SAS0 |
Slot1 PCI 33MHz |
| JPUSB3 | |
|
| ||
Floppy | JI2C1 | JI2C2 |
|
BMC JTAG | USB2 USB3 |
| |
|
|
|
| BIOS |
| Intel ICH10R | |
|
|
| South Bridge | |
|
|
| SAS CTRL | |
|
| CLSI 1068E | ||
SAS1 | SAS2 | SAS3 | SAS4 | SAS5 LES2 SAS6 |
|
| D |
|
JPS2
| ||
| USB 6/7 | |
| USB 4/5 | |
JPUSB2 |
| |
JPS1 | JL1 | |
| 1 |
LES1 FAN3
SAS7
FAN4