PMC-Sierra manual Address Pm25LV512 Pm25LV010, A15 A0 A16 A0

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PMC

Pm25LV512/010

 

 

READ: Reading the Pm25LV512/010 via the SO (Serial Output) pin requires the following sequence. After the CE# line is pulled low to select a device, the READ instruction is transmitted via the Sl line followed by the byte address to be read (Refer to Table 7). Upon completion, any data on the Sl line will be ignored. The data (D7-D0) at

the specified address is then shifted out onto the SO line. If only one byte is to be read, the CE# line should be driven high after the data comes out. The READ instruction can be continued since the byte address is automati- cally incremented and data will continue to be shifted out. For the Pm25LV512/010, when the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous READ instruction.

FAST_READ: The device is first selected by driving CE# low. The FAST READ instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCK (Serial Clock). Then the memory contents, at that address, is shifted out on SO (Serial Output), each bit being shifted out, at a maximum frequency fFR, during the falling edge of SCK (Serial Clock).

The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read with a single FAST READ instruction. The FAST READ instruction is terminated by driving CE# high.

PAGE PROGRAM (PG_PROG): In order to program the Pm25LV512/010, two separate instructions must be executed. First, the device must be write enabled via the WREN instruction. Then the PAGE PROGRAM instruc- tion can be executed. Also, the address of the memory location(s) to be programmed must be outside the pro- tected address field location selected by the Block Write Protection Level. During an internal self-timed program- ming cycle, all commands will be ignored except the RDSR instruction.

The PAGE PROGRAM instruction requires the following sequence. After the CE# line is pulled low to select the device, the PAGE PROGRAM instruction is transmitted via the Sl line followed by the address and the data (D7-D0) to be programmed (Refer to Table 7). Programming will start after the CE# pin is brought high. The low-to-high transition of the CE# pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit.

The READY/BUSY status of the device can be determined by initiating a RDSR instruction. If Bit 0 = 1, the program cycle is still in progress. If Bit 0=0, the program cycle has ended. Only the RDSR instruction is enabled during the program cycle. A single PROGRAM instruction programs 1 to 256 consecutive bytes within a page if it is not write protected. The starting byte could be anywhere within the page. When the end of the page is reached, the address will wrap around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. If more than 256 bytes of data are provided, the address counter will roll over on the same page and the previous data provided will be replaced. The same byte cannot be reprogrammed without erasing the whole sector/block first. The Pm25LV512/010 will automatically return to the write disable state at the completion of the PROGRAM cycle.

Note: If the device is not write enabled (WREN) the device will ignore the Write instruction and will return to the standby state, when CE# is brought high. A new CE# falling edge is required to re-initiate the serial

communication.

Table 7. Address Key

Address

Pm25LV512

Pm25LV010

 

 

 

AN

A15 - A0

A16 - A0

 

 

 

Don't Care Bits

A23 - A16

A23 - A17

Programmable Microelectronics Corp.

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Issue Date: February, 2004, Rev: 1.4

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Contents Hardware Data Protection FeaturesGeneral Description Industrial Standard Pin-out and Package 8-pin Jedec SoicPIN Descriptions Connection DiagramsPin Soic Contact Wson Product Ordering Information Block Diagram SPI Chip Block DiagramSerial Interface Description Bus Master and SPI Memory DevicesSerial Interface Description SPI Modes SPI ModesProduct Identification Data Device OperationInstruction Name Instruction Format Hex Code Operation Bit Bit DefinitionLevel Status Register BitsPm25LV010 ProtectedBlocks UnprotectedBlocks Status RegisterAddress Pm25LV512 Pm25LV010 A15 A0 A16 A0Block Address Pm25LV512 Block Pm25LV010 Block Part Number Absolute Maximum RatingsDC and AC Operating Range Pm25LV512/010DC Characteristics Symbol Parameter Condition Min Typ Max UnitsAC Characteristics Symbol Parameter Min Typ Max UnitsAC WAVEFORMS1 Hold Timing Typ Max Units ConditionsWren Timing Timing DiagramsRdid Timing Wrdi TimingWrsr Timing Rdsr TimingRead Timing Fast Read Timing Program TimingBlock Erase Timing Sector Erase TimingChip Erase Timing Parameter Unit Typ Reliability CharacteristicsPROGRAM/ERASE Performance RemarksPackage Type Information Top View Side View Bottom View Revision History Date Revision No Description of Changes

Pm25LV512, Pm25LV010 specifications

PMC-Sierra is renowned for its high-performance semiconductor solutions, and the PM25LV010 and PM25LV512 are standout products in their lineup of serial NOR flash memory devices. These memory chips are specifically designed for a range of applications that include networking, storage, and consumer electronics, providing reliable performance and efficient data storage.

The PM25LV010 offers 1 megabit of storage capacity, while the PM25LV512 provides 512 kilobits. Both devices feature a simple serial interface that allows for quick and easy connections to various microcontrollers and digital signal processors. This makes them particularly attractive for systems that require fast access to stored data and simplified design architecture.

One of the primary features of the PM25LV010 and PM25LV512 is their high-speed read capability. With access times as low as 45 nanoseconds, these chips enable rapid data retrieval, ensuring that systems can operate effectively without bottlenecks caused by slow memory access. This is particularly crucial in applications where real-time data processing is essential, such as in communications systems or digital signal processing.

In terms of technology, both devices utilize advanced CMOS manufacturing processes that enhance their reliability and performance. They offer flexibility in programming and erasing, with full chip erase functionality and the ability to program data on a page basis. This allows for efficient updates to the stored information without the need to erase large sections of memory.

Power efficiency is another critical aspect of the PM25LV010 and PM25LV512. These devices consume very little power during both active and standby modes, making them suitable for battery-operated devices and energy-sensitive applications. Their low power consumption ensures extended operation time, which is a significant advantage in portable consumer electronics.

Additionally, both chips are designed with robust security features that aid in protecting sensitive data from unauthorized access. They support a variety of locking and protection mechanisms, ensuring that critical information remains confidential.

In summary, the PMC-Sierra PM25LV010 and PM25LV512 serial NOR flash memory devices merge high-speed performance, low power consumption, and advanced security, making them excellent choices for diverse applications in the modern digital landscape. Their design and technology cater to the growing demand for efficient, reliable, and secure memory solutions in today's rapidly evolving electronic ecosystems.
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