Maxim DS5001FP specifications Connection to 128k x 8 Sram

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DS5001FP

Figure 5 illustrates a typical memory connection for a system using a 128kB SRAM. Note that in this configuration, both program and data are stored in a common RAM chip Figure 6 shows a similar system with using two 32kB SRAMs. The byte-wide address bus connects to the SRAM address lines. The bidirectional byte-wide data bus connects the data I/O lines of the SRAM.

Figure 5. CONNECTION TO 128k x 8 SRAM

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Contents DS5001FP 128k Soft Microprocessor Chip FeaturesOrdering Information DescriptionBlock Diagram PIN Description Signal Description MqfpMsel Memory Organization Instruction SETMemory MAP in Partitionable Mode PM = Memory MAP with PES = Connection to 128k x 8 Sram DS5001FP Connection to 64k x 8 Sram Power ManagementAbsolute Maximum Ratings DC CharacteristicsDC Characteristics MAX Units AC Characteristics Expanded BUS Mode Timing SpecificationsDS5001FP Expanded DATA-MEMORY Write Cycle External Clock Timing External Clock DrivePower Cycle Timing Power Cycle TimeSerial Port TIMING, Mode BYTE-WIDE ADDRESS/DATA BUS Timing BYTE-WIDE BUS Timing Parameter Symbol MIN MAX UnitsAC Characteristics AC CHARACTERISTICS, DMARPC Timing Mode DS5001FP PIN Mqfp PIN Mqfp Revision History