Cypress CY7B9911V manual Package Diagram, Pin Plastic Leaded Chip Carrier J65

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CY7B9911V 3.3V RoboClock+™

Package Diagram

Figure 10. 32-Pin Plastic Leaded Chip Carrier J65

51-85002-*B

Document Number: 38-07408 Rev. *D

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Contents Logic Block Diagram FeaturesFunctional Description Cypress Semiconductor Corporation 198 Champion CourtSignal Name Description Pin ConfigurationPin Definitions Block Diagram Description Typical Outputs with FB Connected to a Zero Skew Output Test ModeZero Skew and Zero Delay Clock Driver Operational Mode DescriptionsInverted Output Connections Multi-Function Clock Driver Maximum Ratings Electrical CharacteristicsOperating Range RangeCapacitance Switching Characteristics 5 OptionAC Test Loads and Waveforms Parameter Description CY7B9911V-7 Unit Min Typ Max Switching Characteristics 7 OptionAC Timing Diagrams Accuracy ps Ordering Code Package Type Operating Range Ordering InformationPb-Free CY7B9911V-5JXCTPin Plastic Leaded Chip Carrier J65 Package DiagramDocument History Issue Date Orig. Description of Change