Cypress CY7B9911V manual AC Timing Diagrams

Page 11

CY7B9911V 3.3V RoboClock+™

AC Timing Diagrams

tREF		tRPWL
tRPWH
REF
tPD	tODCV	tODCV
FB
Q
tSKEWPR,		tSKEWPR,
tSKEW0,1		tSKEW0,1

OTHER Q

tSKEW2

INVERTED Q

tSKEW3,4

tSKEW3,4

REF DIVIDED BY 2

tSKEW1,3, 4

tJR

tSKEW2

tSKEW3,4

tSKEW2,4

REF DIVIDED BY 4

Document Number: 38-07408 Rev. *D

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesLogic Block Diagram Functional DescriptionPin Definitions Pin ConfigurationSignal Name Description Block Diagram Description Typical Outputs with FB Connected to a Zero Skew Output Test ModeZero Skew and Zero Delay Clock Driver Operational Mode DescriptionsInverted Output Connections Multi-Function Clock Driver Range Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Loads and Waveforms Switching Characteristics 5 OptionCapacitance Parameter Description CY7B9911V-7 Unit Min Typ Max Switching Characteristics 7 OptionAC Timing Diagrams CY7B9911V-5JXCT Ordering InformationAccuracy ps Ordering Code Package Type Operating Range Pb-FreePin Plastic Leaded Chip Carrier J65 Package DiagramDocument History Issue Date Orig. Description of Change