Cypress CY7B9911V manual Test Mode, Typical Outputs with FB Connected to a Zero Skew Output

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CY7B9911V 3.3V RoboClock+™

Figure 1 shows the typical outputs with FB connected to a zero skew output.[4]

Figure 1. The Typical Outputs with FB Connected to a Zero Skew Output

 

 

U

U

U

U

U

U

 

U

U

U

U

U

U

 

 

– 6t

– 5t

– 4t

– 3t

– 2t

– 1t

 

+1t

+2t

+3t

+4t

+5t

+6t

 

 

0

0

0

0

0

0

0

0

0

0

0

0

0

 

 

t

t

t

t

t

t

t

t

t

t

t

t

t

 

 

FB Input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REFInput

 

 

 

 

 

 

 

 

 

 

 

 

1Fx

3Fx

 

 

 

 

 

 

 

 

 

 

 

 

 

2Fx

4Fx

 

 

 

 

 

 

 

 

 

 

 

 

 

(N/A)

LM

– 6tU

 

 

 

 

 

 

 

 

 

 

 

 

LL

LH

– 4tU

 

 

 

 

 

 

 

 

 

 

 

 

LM

(N/A)

– 3tU

 

 

 

 

 

 

 

 

 

 

 

 

LH

ML

– 2tU

 

 

 

 

 

 

 

 

 

 

 

 

ML

(N/A)

– 1tU

 

 

 

 

 

 

 

 

 

 

 

 

MM

MM

0tU

 

 

 

 

 

 

 

 

 

 

 

 

MH

(N/A)

+1tU

 

 

 

 

 

 

 

 

 

 

 

 

HL

MH

+2tU

 

 

 

 

 

 

 

 

 

 

 

 

HM

(N/A)

+3tU

 

 

 

 

 

 

 

 

 

 

 

 

HH

HL

+4tU

 

 

 

 

 

 

 

 

 

 

 

 

(N/A)

HM

+6tU

 

 

 

 

 

 

 

 

 

 

 

 

(N/A)

LL/HH

DIVIDED

 

 

 

 

 

 

 

 

 

 

 

 

(N/A)

HH

INVERT

 

 

 

 

 

 

 

 

 

 

 

 

Test Mode

The TEST input is a three level input. In normal system operation, this pin is connected to ground, allowing the CY7B9911V to operate as described in “Block Diagram Description” on page 3. For testing purposes, any of the three level inputs can have a removable jumper to ground or be tied LOW through a 100W resistor. This enables an external tester to change the state of these pins.

If the TEST input is forced to its MID or HIGH state, the device operates with its internal phase locked loop disconnected, and input levels supplied to REF directly control all outputs. Relative output-to-output functions are the same as in normal mode.

In contrast with normal operation (TEST tied LOW), all outputs function based only on the connection of their own function select inputs (xF0 and xF1) and the waveform characteristics of the REF input.

Note

4. FB connected to an output selected for “zero” skew (that is, xF1 = xF0 = MID).

Document Number: 38-07408 Rev. *D

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Contents Features Logic Block DiagramFunctional Description Cypress Semiconductor Corporation 198 Champion CourtSignal Name Description Pin ConfigurationPin Definitions Block Diagram Description Test Mode Typical Outputs with FB Connected to a Zero Skew OutputOperational Mode Descriptions Zero Skew and Zero Delay Clock DriverInverted Output Connections Multi-Function Clock Driver Electrical Characteristics Maximum RatingsOperating Range RangeCapacitance Switching Characteristics 5 OptionAC Test Loads and Waveforms Switching Characteristics 7 Option Parameter Description CY7B9911V-7 Unit Min Typ MaxAC Timing Diagrams Ordering Information Accuracy ps Ordering Code Package Type Operating RangePb-Free CY7B9911V-5JXCTPackage Diagram Pin Plastic Leaded Chip Carrier J65Issue Date Orig. Description of Change Document History