Cypress CY7C107B AC Test Loads and Waveforms, Switching Characteristics5 Over the Operating Range

CY7C107B

CY7C1007B

AC Test Loads and Waveforms

5V	R1 480Ω	5V	R1 480Ω
				3.0V

ALL INPUT PULSES

OUTPUT						OUTPUT
										10%
30 pF					R2		5 pF		R2	GND
INCLUDING				255Ω		INCLUDING			255Ω	≤ 3 ns
JIG AND							JIG AND
SCOPE		(a)					SCOPE	(b)
								107-3
Equivalent to:			THÉ VENIN EQUIVALENT
	OUTPUT			167Ω			1.73V

90%

90%

10%

≤ 3 ns

107-4

Switching Characteristics[5] Over the Operating Range

			7C107B-12		7C107B-15		7C107B-20		7C107B-25		7C107B-35
			7C1007B-12		7C1007B-15		7C1007B-20		7C1007B-25		7C1007B-35
Parameter		Description	Min.	Max.	Min.	Max.	Min.	Max.	Min.	Max.	Min.	Max.	Unit
READ CYCLE
tRC	Read Cycle Time		12		15		20		25		35		ns
tAA	Address to Data Valid			12		15		20		25		35	ns
tOHA	Data Hold from Address		3		3		3		3		3		ns
	Change
tACE		LOW to Data Valid		12		15		20		25		35	ns
	CE
tLZCE		LOW to Low Z[6]	3		3		3		3		3		ns
	CE
tHZCE		HIGH to High Z[6, 7]		6		7		8		10		10	ns
	CE
tPU		LOW to Power-Up	0		0		0		0		0		ns
	CE
tPD		HIGH to Power-Down		12		15		20		25		35	ns
	CE
WRITE CYCLE[8]
tWC	Write Cycle Time		12		15		20		25		35		ns
tSCE		LOW to Write End	10		12		15		20		25		ns
	CE
tAW	Address Set-Up to Write		10		12		15		20		25		ns
	End
tHA	Address Hold from Write		0		0		0		0		0		ns
	End
tSA	Address Set-Up to Write		0		0		0		0		0		ns
	Start
tPWE		Pulse Width	10		12		15		20		25		ns
	WE
tSD	Data Set-Up to Write End		7		8		10		15		20		ns
tHD	Data Hold from Write End		0		0		0		0		0		ns
tLZWE		HIGH to Low Z[6]	3		3		3		3		3		ns
	WE
tHZWE		LOW to High Z[6, 7]		6		7		8		10		10	ns
	WE

Notes:

5.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance.

6.At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device.

7.tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.

8.The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.

Document #: 38-05030 Rev. ** Page 4 of 9

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