Cypress CY7C1007BN, CY7C107BN AC Test Loads and Waveforms, Parameter Description Unit Min Max

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CY7C107BN

CY7C1007BN

AC Test Loads and Waveforms

5V

 

 

 

 

R1 480Ω

5V

 

 

 

 

R1 480Ω

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.0V

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10%

 

 

 

 

30 pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R2

5 pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R2

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INCLUDING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

255Ω

INCLUDING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

255Ω

 

≤ 3 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JIG AND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JIG AND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCOPE

(a)

SCOPE

(b)

 

 

 

 

 

 

 

ALL INPUT PULSES

90%

90%

10%

≤ 3 ns

Equivalentto:

THÉVENIN EQUIVALENT

 

 

167Ω

OUTPUT

 

 

 

 

1.73V

 

 

 

Switching Characteristics[5] Over the Operating Range

 

 

 

 

 

 

7C107BN-15

 

 

 

 

 

 

7C1007BN-15

 

Parameter

 

 

 

Description

 

 

 

Unit

 

 

 

Min.

 

Max.

 

 

 

 

 

 

 

 

 

READ CYCLE

 

 

 

 

 

 

 

 

 

 

 

 

 

tRC

 

Read Cycle Time

15

 

 

ns

tAA

 

Address to Data Valid

 

 

15

ns

tOHA

 

Data Hold from Address Change

3

 

 

ns

tACE

 

 

 

LOW to Data Valid

 

 

15

ns

CE

 

tLZCE

 

 

 

LOW to Low Z[6]

3

 

 

ns

CE

 

 

tHZCE

 

 

 

HIGH to High Z[6, 7]

 

 

7

ns

CE

 

tPU

 

 

 

LOW to Power-Up

0

 

 

ns

CE

 

 

tPD

 

 

 

HIGH to Power-Down

 

 

15

ns

CE

 

WRITE CYCLE[8]

 

 

 

 

 

 

 

 

tWC

 

Write Cycle Time

15

 

 

ns

tSCE

 

 

 

LOW to Write End

12

 

 

ns

CE

 

 

tAW

 

Address Set-Up to Write End

12

 

 

ns

tHA

 

Address Hold from Write End

0

 

 

ns

tSA

 

Address Set-Up to Write Start

0

 

 

ns

tPWE

 

 

 

Pulse Width

12

 

 

ns

WE

 

 

tSD

 

Data Set-Up to Write End

8

 

 

ns

tHD

 

Data Hold from Write End

0

 

 

ns

tLZWE

 

 

 

HIGH to Low Z[6]

3

 

 

ns

WE

 

 

tHZWE

 

 

 

LOW to High Z[6, 7]

 

 

7

ns

WE

 

Notes:

5.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance.

6.At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device.

7.tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.

8.The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.

Document #: 001-06426 Rev. **

Page 3 of 7

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Contents Functional Description FeaturesLogic Block Diagram Pin ConfigurationElectrical Characteristics Over the Operating Range Maximum RatingsCapacitance4 Switching Characteristics5 Over the Operating Range AC Test Loads and WaveformsParameter Description Unit Min Max Switching Waveforms Read Cycle NoWrite Cycle No CE Controlled13 Ordering Information Mode PowerOrdering Code Package Package Type Operating Diagram Range Truth TablePackage Diagrams Lead 400-Mil Molded SOJLead 300-Mil Molded SOJ Issue Orig. Description of Change Date 423847 New Data SheetDocument History

CY7C107BN, CY7C1007BN specifications

The Cypress CY7C107BN and CY7C1007BN are versatile synchronous static RAM (SRAM) devices that are widely used in various electronic applications, including networking, telecommunications, and consumer electronics. These devices are designed to meet the demands for high-speed memory accesses while providing low power consumption and high reliability, making them an ideal choice for designers seeking efficient memory solutions.

One of the main features of the CY7C107BN and CY7C1007BN is their high-speed access time. Both chips offer access times as fast as 10 nanoseconds, which allows devices using these memories to process data at impressive rates. This speed is particularly beneficial for applications requiring rapid read and write operations, such as cache memory or data buffering in high-performance computing environments.

In terms of memory density, the CY7C107BN offers a capacity of 1 Megabit, while the CY7C1007BN provides a greater capacity of 2 Megabits. This makes both chips suitable for varying storage requirements, allowing designers to select the appropriate size based on their application's memory needs. The memory architecture of these SRAMs consists of a static cell design, which ensures data retention without the need for refresh cycles, contrasting with dynamic RAM (DRAM) technologies. This characteristic not only simplifies system design but enhances performance and reliability.

The Cypress SRAMs are implemented in a single 5-volt power supply range, facilitating compatibility with a wide range of existing systems. Their low standby current consumption is another notable advantage, enabling battery-operated devices to operate for extended periods without significant power drain.

Moreover, the CY7C107BN and CY7C1007BN incorporate advanced CMOS technology, which contributes to their low power dissipation and high noise immunity. Designers appreciate the integration and ease of implementation made possible by 10 leading-edge package options available for these devices.

Additionally, both memory chips support common SRAM functionalities, including asynchronous read and write controls, enabling straightforward interfacing with microcontrollers and digital signal processors. With built-in features for write enable, output enable, and chip select, these SRAMs facilitate flexible memory management and control in diverse applications.

In summary, the Cypress CY7C107BN and CY7C1007BN SRAMs represent robust and efficient memory solutions that offer high speeds, low power consumption, and significant reliability. Their features make them suitable for a wide range of electronic applications, solidifying their position as trusted components in the evolving landscape of semiconductor technologies.