Cypress CY7C1007BN manual Features, Functional Description, Logic Block Diagram, Selection Guide

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Features

High speed

— tAA = 15 ns

CMOS for optimum speed/power

Automatic power-down when deselected

TTL-compatible inputs and outputs

CY7C107BN

CY7C1007BN

1M x 1 Static RAM

Functional Description

The CY7C107BN and CY7C1007BN are high-performance CMOS static RAMs organized as 1,048,576 words by 1 bit. Easy memory expansion is provided by an active LOW Chip Enable (CE) and three-state drivers. These devices have an automatic power-down feature that reduces power consumption by more than 65% when deselected.

Writing to the devices is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the input pin (DIN) is written into the memory location specified on the address pins (A0 through A19).

Reading from the devices is accomplished by taking Chip Enable (CE) LOW while Write Enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the data output (DOUT) pin.

The output pin (DOUT) is placed in a high-impedance state when the device is deselected (CE HIGH) or during a write operation (CE and WE LOW).

The CY7C107BN is available in a standard 400-mil-wide SOJ; the CY7C1007BN is available in a standard 300-mil-wide SOJ

Logic Block Diagram

 

 

 

 

 

 

 

 

 

 

 

 

 

DIN

A0

 

 

INPUT BUFFER

 

 

DECODERROW

 

 

 

 

 

 

 

AMPSSENSE

 

A7

 

 

 

 

 

 

 

 

A1

 

 

 

 

 

 

 

 

 

 

A2

 

 

 

 

 

 

 

 

 

 

A3

 

 

 

 

 

 

 

 

 

 

A4

 

 

512 x 2048

 

 

 

A5

 

 

 

ARRAY

 

 

DOUT

A6

 

 

 

 

 

 

 

 

 

A8

 

 

 

 

 

 

 

 

 

 

 

 

 

COLUMN

 

 

POWER

 

 

 

 

 

 

DOWN

CE

 

 

 

DECODER

 

 

 

 

 

 

 

 

 

 

 

9

10 11

12 13

14

15

16

17 18

19

 

WE

 

A

 

 

A A A A A A A A A A

 

 

Pin Configuration

 

 

SOJ

 

 

Top View

 

A10

1

28

VCC

A11

2

27

A

A12

3

26

A9

A13

4

25

A8

A14

 

24

7

5

A6

23

A15

6

A5

22

NC

7

A4

21

A16

8

NC

20

A17

9

A3

19

A

10

A

A18

11

18

A2

DOUT19

12

17

A01

WE

13

16

DIN

GND

14

15

CE

Selection Guide

 

 

7C107BN-15

 

 

 

 

7C1007BN-15

 

 

Maximum Access Time (ns)

 

15

 

 

Maximum Operating Current (mA)

 

80

 

 

Maximum CMOS Standby Current ISB2 (mA)

 

2

 

 

Cypress Semiconductor Corporation

198 Champion Court • San Jose, CA 95134-1709

408-943-2600

Document #: 001-06426 Rev. **

 

Revised February 1, 2006

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Contents Logic Block Diagram FeaturesPin Configuration Functional DescriptionMaximum Ratings Electrical Characteristics Over the Operating RangeCapacitance4 AC Test Loads and Waveforms Switching Characteristics5 Over the Operating RangeParameter Description Unit Min Max Read Cycle No Switching WaveformsWrite Cycle No CE Controlled13 Ordering Code Package Package Type Operating Diagram Range Mode PowerTruth Table Ordering InformationLead 400-Mil Molded SOJ Package DiagramsLead 300-Mil Molded SOJ New Data Sheet Issue Orig. Description of Change Date 423847Document History

CY7C107BN, CY7C1007BN specifications

The Cypress CY7C107BN and CY7C1007BN are versatile synchronous static RAM (SRAM) devices that are widely used in various electronic applications, including networking, telecommunications, and consumer electronics. These devices are designed to meet the demands for high-speed memory accesses while providing low power consumption and high reliability, making them an ideal choice for designers seeking efficient memory solutions.

One of the main features of the CY7C107BN and CY7C1007BN is their high-speed access time. Both chips offer access times as fast as 10 nanoseconds, which allows devices using these memories to process data at impressive rates. This speed is particularly beneficial for applications requiring rapid read and write operations, such as cache memory or data buffering in high-performance computing environments.

In terms of memory density, the CY7C107BN offers a capacity of 1 Megabit, while the CY7C1007BN provides a greater capacity of 2 Megabits. This makes both chips suitable for varying storage requirements, allowing designers to select the appropriate size based on their application's memory needs. The memory architecture of these SRAMs consists of a static cell design, which ensures data retention without the need for refresh cycles, contrasting with dynamic RAM (DRAM) technologies. This characteristic not only simplifies system design but enhances performance and reliability.

The Cypress SRAMs are implemented in a single 5-volt power supply range, facilitating compatibility with a wide range of existing systems. Their low standby current consumption is another notable advantage, enabling battery-operated devices to operate for extended periods without significant power drain.

Moreover, the CY7C107BN and CY7C1007BN incorporate advanced CMOS technology, which contributes to their low power dissipation and high noise immunity. Designers appreciate the integration and ease of implementation made possible by 10 leading-edge package options available for these devices.

Additionally, both memory chips support common SRAM functionalities, including asynchronous read and write controls, enabling straightforward interfacing with microcontrollers and digital signal processors. With built-in features for write enable, output enable, and chip select, these SRAMs facilitate flexible memory management and control in diverse applications.

In summary, the Cypress CY7C107BN and CY7C1007BN SRAMs represent robust and efficient memory solutions that offer high speeds, low power consumption, and significant reliability. Their features make them suitable for a wide range of electronic applications, solidifying their position as trusted components in the evolving landscape of semiconductor technologies.