Cypress CY7C1334H manual Document History, REV ECN no, Issue Date Orig. Description of Change

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CY7C1334H

Document History Page

Document Title: CY7C1334H 2-Mbit (64K x 32) Pipelined SRAM with NoBL™ Architecture

Document Number: 38-05678

REV.	ECN NO.	Issue Date	Orig. of	Description of Change
REV.	ECN NO.	Issue Date	Change	Description of Change

**	347357	See ECN	PCI	New Data Sheet

*A	424820	See ECN	RXU	Changed address of Cypress Semiconductor Corporation on Page# 1 from
				“3901 North First Street” to “198 Champion Court”
				Changed Three-State to Tri-State.
				Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
				Electrical Characteristics Table.
				Modified test condition from VDDQ < VDD to VDDQ < VDD
				Replaced Package Name column with Package Diagram in the Ordering
				Information table.
				Replaced Package Diagram of 51-85050 from A to B
*B	459347	See ECN	NXR	Converted from Preliminary to Final
				Included 2.5V I/O option
				Updated the Ordering Information table.

Document #: 38-05678 Rev. *B

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Contents Logic Block Diagram FeaturesCypress Semiconductor Corporation Maximum Access Time tCO Maximum Operating Current IDD Pin ConfigurationSelection Guide 166 MHz 133 MHz UnitPin Definitions Functional Overview First Second Third Fourth Address A1, A0 Interleaved Burst Address Table Mode = Floating or VDDFirst Second Third Fourth Address A1, A0 Operation Used ADV/LD CEN CLKWrite Cycle Description2 ZZ Mode Electrical CharacteristicsFunction BW D BW C BW B BW aOperating Range Maximum RatingAmbient Range Thermal Resistance11 Capacitance11AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 12 Read/Write Timing18, 19 Switching WaveformsAddress A1 A2 DON’T CareNOP, STALL, and Deselect Cycles18, 19 ZZ Mode Timing22DA4 Ordering Information Package DiagramPin Tqfp 14 x 20 x 1.4 mm Document History Issue Date Orig. Description of ChangeREV ECN no