Cypress CY7C1018DV33 manual Features, Functional Description1, Logic Block Diagram

CY7C1018DV33

1-Mbit (128K x 8) Static RAM

Features

•Pin- and function-compatible with CY7C1018CV33

•High speed

—tAA = 10 ns

•Low Active Power

—ICC = 60 mA @ 10 ns

•Low CMOS Standby Power

—ISB2 = 3 mA

•2.0V Data retention

•Automatic power-down when deselected

•CMOS for optimum speed/power

•Center power/ground pinout

•Easy memory expansion with CE and OE options

•Available in Pb-free 32-pin 300-Mil wide Molded SOJ

Functional Description[1]

The CY7C1018DV33 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected.

Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16).

Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW).

The CY7C1018DV33 is available in Pb-free 32-pin 300-Mil wide Molded SOJ.

Logic Block Diagram											Pin Configuration
													SOJ
												Top View
											A0	1	32	A16
											A1	2	31	A15
											A2	3	30	A
											A3			14
										I/O0		4	29	A13
	INPUTBUFFER										CE	5	28	OE
										I/O	I/O0	6	27	I/O
														7
A0	ROW DECODER									1	I/O1	7	26	I/O6
A1									SENSE AMPS	I/O	VCC	8	25	V
A2										2	VSS		24	SS
A										I/O3		9		VCC
A43		128K × 8									I/O2	10	23	I/O5
A5			ARRAY							I/O4	I/O3	11	22	I/O4
A6											WE	12	21	A
A7														12
											A4	13	20	A11
A8										I/O5
											A5	14	19	A10
CE			COLUMN						POWER	I/O6	A6	15	18	A9
WE											A	16	17	A8
			DECODER						DOWN		7
										I/O7
OE
	9	10	11	12	13	14	15	16
	A A A A A A A A
Note

1. For guidelines on SRAM system designs, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.

Cypress Semiconductor Corporation	• 198 Champion Court • San Jose, CA 95134-1709	•	408-943-2600
Document #: 38-05465 Rev. *D	Revised November 8, 2006

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