Cypress manual November 7, CY8CTMG200 and CY8CTST200 Errata Summary

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CY8CTMG200, CY8CTST200

November 7, 2008

Errata Document for TrueTouch® CY8CTMG200, CY8CTST200

This document describes the errata for the TrueTouch® CY8CTMG200 and CY8CTST200. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Compare this document to the device’s data sheet for a complete functional description.

Contact your local Cypress Sales Representative if you have questions.

CY8CTMG200 and CY8CTST200 Errata Summary

The following Errata items apply to the CY8CTMG200 and CY8CTST200 datasheets 001-47603 and 001-47602.

1. Latch-up susceptibility when maximum I/O sink current exceeded

nPROBLEM DEFINITION

P1[3], P1[6], and P1[7] pins are susceptible to latch-up when the I/O sink current exceeds 25 mA per pin on these pins.

nPARAMETERS AFFECTED

LU – Latch-up Current. Per JESD78A, the maximum allowable latch-up current per pin is 100 mA. Cypress internal specification is 200 mA latch-up current limit.

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TRIGGER CONDITION(S)

Latch-up occurs when both of the following two conditions are met:

A.The offending I/O is externally connected to a voltage higher than the I/O high state, causing a current to flow into the pin that exceeds 25 mA

B.A Port1 I/O adjacent (P1[1], P1[4] and P1[5] respectively) to the offending I/O is connected to a voltage lower than the I/O low state, causing a signal that drops below Vss (signal undershoot), causing a current greater than 200 mA to flow out of the pin

SCOPE OF IMPACT

The trigger conditions outlined above exceed the maximum ratings specified in the CY8CTMG200 and CY8CTST200 datasheets 001-47603 and 001-47602.

WORKAROUND

Add a series resistor >300Ω to P1[3], P1[6], and P1[7] pins to restrict current to within latch-up limits.

FIX STATUS

This issue will be corrected in the next new silicon revision.

The following Errata item applies only to the CY8CTMG200-48LTXI, CY8CTST200-48LTXI, and CY8CTMG200- 00LTXI, parts on the 001-47603 and 001-47602 Datasheets.

2. Does not meet USB 2.0 specification for D+ and D- rise/fall matching when supply voltage is under 3.3V

nPROBLEM DEFINITION

Rising to falling rate matching of the USB D+ and D- lines has a corner case at lower supply voltages, such as those under 3.3V.

nPARAMETERS AFFECTED

Rising to falling rate matching of the USB data lines.

nTRIGGER CONDITION(S)

Operating the VCC supply voltage at the low end of the chip’s specification (under 3.3V) may cause a missmatch in the rising to falling rate.

Cypress Semiconductor Corporation

198 Champion Court

San Jose, CA 95134

408.943.2600

November 7, 2008

 

Document No. 001-49988 Rev. **

 

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Contents CY8CTMG200 and CY8CTST200 Errata Summary November 7CY8CTMG200, CY8CTST200 DTB Document History

CY8CTMG200, CY8CTST200 specifications

The Cypress CY8CTST200 and CY8CTMG200 are innovative components within Cypress Semiconductor's renowned CapSense product family, designed to enhance user interface experiences through capacitive touch technology. These devices are widely used in consumer electronics, automotive controls, and industrial applications, offering a versatile solution to modern interface demands.

One of the main features of the CY8CTST200 is its ability to support both proximity sensing and touch control, enabling users to interact with devices through simple gestures and touch inputs. This versatility allows for the development of highly intuitive interfaces that can be easily integrated into various products, ranging from home appliances to mobile devices.

The CY8CTMG200, on the other hand, focuses on providing robust multi-touch support and improved noise filtering capabilities. This makes it an ideal choice for applications requiring precision touch responsiveness, such as smartphones and tablets. The device's advanced algorithms allow for the simultaneous detection of multiple touch points, ensuring a seamless user experience, even in challenging environments.

Both devices leverage Cypress’s patented CapSense technology, which employs capacitive sensing principles to detect touch events. This technology is known for its low power consumption, making it suitable for battery-operated devices. Additionally, the devices offer customizable settings, allowing developers to fine-tune sensitivity and performance to meet specific application requirements.

Another notable characteristic of the CY8CTST200 and CY8CTMG200 is the integration of their functionality with Cypress's PSoC (Programmable System-on-Chip) architecture. This integration allows engineers to utilize a single chip for both sensing and processing, significantly reducing BOM (Bill of Materials) costs and simplifying the overall design process.

Both models are equipped with advanced noise immunity features, enabling reliable operation in environments with electrical noise, such as industrial machinery or automotive applications. Their ability to ignore false touches ensures that only intentional interactions are registered, thereby enhancing user experience and reliability.

In summary, the Cypress CY8CTST200 and CY8CTMG200 devices stand out for their advanced capacitive touch capabilities, low power consumption, and integration with PSoC technology. These features make them ideal choices for developers looking to create innovative and user-friendly interfaces across a variety of applications, driving the future of touch technology in consumer and industrial markets.