Cypress CY62256 manual Features, Cypress Semiconductor Corporation, Inputbuffer, Column, Decoder

CY62256

256K (32K x 8) Static RAM

Features Functional Description[1]

•High speed: 55 ns and 70 ns

•Voltage range: 4.5V–5.5V operation

•Low active power (70 ns, LL version)

—275 mW (max.)

•Low standby power (70 ns, LL version)

—28 ∝ W (max.)

•Easy memory expansion with CE and OE features

•TTL-compatible inputs and outputs

•Automatic power-down when deselected

•CMOS for optimum speed/power

•Package available in a standard 450-mil-wide (300-mil body width) 28-lead narrow SOIC, 28-lead TSOP-1, 28-lead reverse TSOP-1, and 600-mil 28-lead PDIP packages

The CY62256 is a high-performance CMOS static RAM organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and three-state drivers. This device has an automatic power-down feature, reducing the power consumption by 99.9% when deselected.

An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins.

The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH.

Logic Block Diagram

	INPUTBUFFER						I/O0
A10	DECODERROW						I/O1
						AMPSSENSE
A3
A9							I/O2
A8
A7							I/O3
A6		512 x 512
A5		ARRAY					I/O4
A4
A2							I/O5
CE						POWER	I/O6
WE		COLUMN
						DOWN
		DECODER
							I/O7
OE
	14	13	12	11	1	0
	A	A	A A		A	A

Note:

1.For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation	• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05248 Rev. *B	Revised August 27, 2002