National Instruments DP8400 specifications Table V. Error Flags after Normal Read

A key advantage of the DP8400 is that it has three error flags detailing the type of error occurrence. These are gen- erated using the syndrome word in the manner shown in Figure 11 . The resulting error type identifications are shown in Table V. The three error flags allow complete error type identification, plus the unique determination of double bit errors, which will be key during the discussion of double bit error correction. Also, on a memory read, the DP8400 gen- erates byte parity bits for transmission to the processor along with the data.

				TL/F/5012 – 15
	TABLE V. Error Flags after Normal Read
AE		E1	E0	Error Type
0		0	0	No Error
1		1	0	Single Check Bit Error
1		1	1	Single Data Error
1		0	0	Double-Bit Error
		All Others		Invalid Conditions

There are two basic memory read methods that may be used with the DP8400. The first is shown in Figure 9b and is called the error monitoring method. Here, the read data is assumed to be correct and the processor immediately acts on the data. If the DP8400 detects an error, the processor is interrupted using the any error flag (AE). Using this method, there is no detection delay in most memory reads since errors seldom occur, but when an error does occur, the processor must be capable of accepting an interrupt and a read cycle extension to obtain the corrected data from the DP8400.

A second approach is called the always correct method, Figure 9c . In this case, the data is always assumed to be in error and the processor always waits for the DP8400 to ana- lyze whether an error exits. Then the corrected or un- changed data is read from the DP8400. Although this meth- od results in longer memory read time, every memory read will always be of the same delay except when a double error occurs. The selection of which method to use depends on many factors, including the processor, system structure, and performance.

Double Bit Error Correct

The probability of double bit errors in DRAM systems is rela- tively low, but as memory array sizes grow, the occurrence of these error types must be considered. Adopting certain practices, such as rewriting a memory location whenever an error is detected, or using ‘‘memory scrubbing’’ techniques, can significantly reduce the probability of a double soft error occurrence. Memory scrubbing is when the system, during low usage, actually accesses memory solely for the purpose of identifying and correcting single soft errors. This is an important technique if there are segments of the memory that are not always being accessed so that soft error occur- rences would not be quickly found.

The occurrence of a double error comprising one soft and one hard must now be considered. This type of error has a higher probability than two soft errors. The hard error may be due to a catastrophic chip failure, and a subsequent soft error will create two errors. This can be a source of concern since most error correction chips cannot handle double er- rors of this type. Therefore, most systems will ‘‘crash’’ when a catastrophic chip failure is coupled with a soft error in the same memory address.

The DP8400 has been designed to handle just such an oc- currence. It can correct any double bit error, as long as at least one of the errors is a hard error. The DP8400 does this without the need for extra hardware required for the basic double bit detect/single bit correct system implementation. This method is called the double complement correct tech- nique and is demonstrated in Figure 12 using a 4-bit data word for simplicity. In this example, a single hard error is located in the most significant bit of a particular memory location and a soft error occurs at the next bit. The position of the errors is not important since the errors may be distrib- uted in either the data or check bit field or both. First, the data word and corresponding check bits are written to this memory location. When a later read of this location occurs, step A, two errors are directly reported by the DP8400 error flags. The system detects this, disables memory; and places the DP8400 in the complement write mode. This causes the previously read data and check bits to be complemented in the DP8400 and written back to the same memory address, step B, writing over the previous soft error. Obviously this does not modify the cell where the hard error exits. The system then reads from the same address again, but this time it places the DP8400 in the complement read mode, step C. The DP8400 again complements the memory data and check bits and generates new check bits based on the new data word. At this point, the chip detects a single bit error in the bit position where the soft error occurred, and using the conventional single error correction procedure, re- turns corrected data to the system, step D.

In the second read, the complement read, the hard error repeats since this bit location again receives a bit which is complemented with respect to itself. But the soft error has been overwritten and does not repeat. Effectively, the mem- ory has complemented the hard bit error position twice and the soft bit error position only once, while the DP8400 com- plements both positions twice. Therefore, after the second read, there is only one error left, the soft error. Since this is now a single error it can be directly corrected.

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