Maxtor 52049H3, 51536H2, 53073H4, 546106 specifications Reset and Interrupt Handling

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HOST SOFTWARE INTERFACE

Reset and Interrupt Handling

Reset Handling

One of three different conditions may cause a reset: power on, hardware reset or software reset. All three cause the interface processor to initialize itself and the Task File registers of the interface. A reset also causes a set of the Busy bit in the Status register. The Busy bit does not clear until the reset clears and the drive completes initialization. Completion of a reset operation does not generate a host interrupt.

Task File registers are initialized as follows:

Error		1
Sector	Count	1
Sector	Number	1
Cylinder Low		0
Cylinder High		0
Drive/Head		0

Interrupt Handling

The drive requests data transfers to and from the host by asserting its IRQ 14 signal. This signal interrupts the host if enabled by bit 1 (IRQ enable) of the Fixed Disk Control register.

Clear this interrupt by reading the Status register, writing the Command register, or by executing a host hardware or software reset.

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Contents Corporate Headquarters REV EC N O SEC Tion Desc Ription ATE U T I O N Before You BeginContents Handling and Installation Product SpecificationsHost Software Interface Interface CommandsAT Interface Description Glossary Service and SupportFigures MaxtorCorporation IntroductionManualOrganization AbbreviationsConventions Product Description KeyFeaturesModel S SP T MAX LB a Apac IT Y Product FeaturesFunctional / Interface CacheManagement MajorHDAComponents CylinderLimitationJumperDescription SubsystemConfigurationJumper Location / Configuration DriveConfiguration ProductSpecificationsPerformanceSpecifications ModelsandCapacitiesAram E TE R Stan D ARD ME T RIC PhysicalDimensionsmaximumPowerModeDefinitions PowerRequirementsEPA Energy Star Compliance EnvironmentalLimitsParam E TE R OP ER AT ING ON- OPE R AT ING ReliabilitySpecificationsShock and Vibration EMC/EMI SafetyRegulatoryComplianceElectro-StaticDischargeESD HandlingandInstallationHardDriveHandlingPrecautions Multi-pack Shipping Container UnpackingandInspectionRepacking PhysicalInstallationHook up Before You BeginStart up Set upATInterfaceDescription InterfaceConnectorPinDescriptionSummary PIN IGN ALPin Description Table PIN Name Signal Name Signal Desc RiptionPIO Timing IM in G Paramet ERS ModeDMATiming Imin G Paramet ERS ModeMode Ultra DMA TimingSustained Ultra DMA Data In Burst Device Terminating an Ultra DMA Data In Burst Initiating an Ultra DMA Data Out Burst Device Pausing an Ultra DMA Data Out Burst Device Terminating an Ultra DMA Data Out Burst POR T EAD WR ITE HostSoftwareInterfaceTask File Registers Conten TS LBA Bits CommandRegister M M a N D N a M E M M a N D code PA R a M E T E R S U S E D SummaryControl Diagnostic Registers Reset and Interrupt Handling InterfaceCommands ReadCommands Read DMA WriteCommands Write Multiple LE VE L ModeSet/CheckCommandsVAL UE DES C RIP Tion VAL UE Omman D Timer VAL UE TIME-OUT Period PowerModeCommandsSleep Mode Or D ENT Desc Ription InitializationCommandsOr D 15- 10, as c urrently defined Initialize Drive Parameters ER ROR Code Desc Ription Seek,FormatandDiagnosticCommandsKey Register A.R.T. CommandSetServicePolicy ServiceandSupportNoQuibbleService SupportFrom Dial Glossary AccesstimeCorrectableerror Fetch Landingzoneorlzone Physicalsector Softerror