EPoX Computer KP6-LA specifications Unexpected Errors

Page 40

Appendix

 

KP6-LA

61

1.

Try to turn on Level 2 cache.

 

Note: If L2 cache is already turned on in POST 3D, this part will be

 

skipped.

 

2.

Set the boot up speed according to Setup setting.

 

3. Last chance for Chipset initialization.

 

4.

Last chance for Power Management initialization. (Green BIOS

 

only)

 

5.

Show the system configuration table.

62

1.

Setup daylight saving according to Setup value.

 

2.

Program the NUM Lock, typematic rate & typematic speed

 

according to Setup setting.

63

1.

If there is any changes in the hardware configuration, update the

 

ESCD information. (PnP BIOS only)

 

2.

Clear memory that have been used.

 

3.

Boot system via INT 19H.

FF

System Booting. This means that the BIOS already pass the control

 

right to the operating system.

B-2 Unexpected Errors:

POST (hex)

DESCRIPTION

B0

If interrupt occurs in protected mode.

B1

Unclaimed NMI occurs.0

A-8

Image 40
Contents 6 LA KP6-LA Technical Support Services Bios UpgradesUser Notice KP6-LA KP6-LA Table of Contents DMI Section Components ChecklistKP6-LAIntroduction Introduction OverviewPentium C. Cartridge Terminology Pentium II ProcessorHardware Monitoring Accelerated Graphics Port AGP or A.G.PDesktop Management Interface DMI Left Blank KP6-LA Form-Factor ATXShield Connector Power-On/Off RemoteSystem Block Diagram System Block DiagramFeatures KP6-LA FeaturesKP6-LA Installation Real Picture MotherboardKP6-LA Detailed Layout Easy Installation Procedure Easy Installation ProcedureSection Configure Jumpers CPU Processor Selection Section System Memory Configuration Memory Layout Simm Module Installation DimmDimm Module Installation InstallationKP6-LA Section Installing a Pentium II Processor ScrewsBottom fin Heatsink Section Device Connectors Please install the motherboard into the chassisJP7 DMI Access DMI AccessLeft Blank Appendix a AppendixTimer & DMA Channels MAP RTC & Cmos RAM MAP Left Blank Appendix B Post CodesInitialization of the Bios Data Area on 40FF Cmos Unexpected Errors Appendix C