American Megatrends MAN-758 manual Optimal and Fail-Safe defaults are Disabled Cont’d

Chipset Setup, Continued

DRAM ECC Mode This option sets the type of system memory checking. The settings are:

Setting	Description
Disabled	No error checking or error reporting is done.
Level I	Multibit errors are detected and reported as parity errors. Single-bit errors are
	correctedbythechipset.Correctedbitsofdatafrommemoryarenotwrittenback
	toDRAMsystemmemory.IfLevel I isselected,theJ27ExternalSMIsoftware
	jumper on the Series 735 board is disabled.
Level II	Multibit errors are detected and reported as parity errors. Single-bit errors are
	correctedbythechipsetandarewrittenbacktoDRAMsystemmemory.
	Ifasoft(correctable)memoryerroroccurs,writingthefixeddatabacktoDRAM
	systemmemorywillresolvetheproblem.MostDRAMerrorsaresofterrors.Ifa
	hard (uncorrectable) error occurs,writing thefixed data back to DRAM system
	memorydoesnotsolvetheproblem.Inthiscase,thesecondtimetheerroroccurs
	in the same location, a Parity Error is reported, indicating an uncorrectable error.
	If Level II is selected, AMIBIOS automatically sets the Standard Power
	Management optioninPowerManagementSetuptoEnabled tomakesure
	thattheSystemManagementInterface(SMI) is enabled. If you do not want to
	enablepowermanagement,settheAdvanced Power Management (APM) option
	to Disabled and set all Power Management Setup timeout options to
	Disabled. Toenable power management, setAdvanced Power Management
	(APM) to Enabled andsetthepowermanagementtimeoutoptionsasdesired.

The following illustrates the difference between Level I and Level II ECC. Suppose a DRAM SIMM has a single bit uncorrectable error. Even writing fixed data to this bit will not remove the error.

Setting	then...
Level I	the data error is fixed during the memory read cycle every time
	the bad bit is accessed and the system continues to run, although
	every time the bad bit is read and corrected, CPU cycles are
	wasted.
Level II	the system tries to write the corrected data back to the bad bit in
	the DRAM SIMM. Since the bad bit in the SIMM cannot be fixed,
	writing data to the bad bit has no effect. The next time the error
	location is read, the chipset will once again find a bad bit. The
	chipset generates a Parity Error, indicating an uncorrectable
	memory error.

The Optimal and Fail-Safe defaults are Disabled.

Cont’d

Chapter 2 WINBIOS Setup 57