Award BIOS Setup Utility
3.1.3.1 DRAM Clock/Drive Control
Move the cursor to this field and press <Enter>. The following screen will appear
Phoenix - AwardBIOS CMOS Setup Utility
DRAM Clock/Drive Control
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| Current FSB Frequency |
| 133MHz |
| Item Help |
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| Current DRAM Frequency |
| 133MHz |
| Menu Level |
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| DRAM Clock |
| By SPD |
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| DRAM Timing |
| By SPD |
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| X SDRAM CAS Latency |
| 2.5 |
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| X Bank Interleave |
| Disabled |
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| X Precharge to Active (Trp) |
| 3T |
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| X Active to Precharge (Tras) |
| 6T |
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| X Active to CMD (Trcd) |
| 3T |
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| X DRAM Command Rate |
| 2T Command |
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| DRAM Burst Len |
| 4 |
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| ↑↓→← Move Enter:Select | ESC:Exit F1:General Help |
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| F5:Previous Values | F7:Optimized Defaults |
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The settings on the screen are for reference only. Your version may not be identical to this one.
Current FSB Frequency
This field shows the detected FSB of the CPU.
Current DRAM Frequency
This field shows the detected frequency of the DRAM.
DRAM Clock
This field is used to select the clock speed of the DIMM.
By SPD The EEPROM on a DIMM has SPD (Serial Presence Detect) data structure that stores information about the module such as the memory type, memory size, memory speed, etc. When this option is selected, the system will run according to the information in the EEPROM.
100 MHz The memory clock speed will run at 200MHz.
133 MHz The memory clock speed will run at 266MHz.
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