DFI PM12-EC, PM12-EL Dram Clock/Drive Control, Current FSB Frequency, Current Dram Frequency

Award BIOS Setup Utility

3.1.3.1 DRAM Clock/Drive Control

Move the cursor to this field and press <Enter>. The following screen will appear

Phoenix - AwardBIOS CMOS Setup Utility

DRAM Clock/Drive Control

Current FSB Frequency		133MHz		Item Help
Current DRAM Frequency		133MHz		Menu Level
DRAM Clock		By SPD
DRAM Timing		By SPD
X SDRAM CAS Latency		2.5
X Bank Interleave		Disabled
X Precharge to Active (Trp)		3T
X Active to Precharge (Tras)		6T
X Active to CMD (Trcd)		3T
X DRAM Command Rate		2T Command
DRAM Burst Len		4
↑↓→← Move Enter:Select	+/-/PU/PD:Value F10:Save		ESC:Exit F1:General Help
F5:Previous Values		F6:Fail-Safe Defaults	F7:Optimized Defaults

The settings on the screen are for reference only. Your version may not be identical to this one.

Current FSB Frequency

This field shows the detected FSB of the CPU.

Current DRAM Frequency

This field shows the detected frequency of the DRAM.

DRAM Clock

This field is used to select the clock speed of the DIMM.

By SPD The EEPROM on a DIMM has SPD (Serial Presence Detect) data structure that stores information about the module such as the memory type, memory size, memory speed, etc. When this option is selected, the system will run according to the information in the EEPROM.

100 MHz The memory clock speed will run at 200MHz.

133 MHz The memory clock speed will run at 266MHz.

3

57