Chapter 6
Specifications
Typical for 25 °C unless otherwise specified.
Specifications in italic text are guaranteed by design.
Analog input
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| Table 1. Analog input specifications |
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A/D converter type | ||
Resolution | 16 bits | |
Number of channels | 32 differential or 64 | |
Input ranges | ±5 V, ±2.5 V, ±1.25 V, ±0.625 V, 0 to 5 V, 0 to 2.5 V, 0 to 1.25 V | |
(software programmable) |
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Polarity | Unipolar/bipolar, software selectable | |
A/D pacing | ! | Internal counter – ASIC |
(software programmable) | ! | External source (A/D external pacer). The total number of sample clocks must be at least |
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| 5 greater than the total number of samples desired. This is required to accommodate the |
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| pipelined architecture of the ADC. |
| ! | Software polled |
Burst mode | Software selectable option. Valid for a fixed input range only. | |
| Burst rate = 667 nS. | |
A/D gate sources | ! | External digital (A/D pacer gate) |
| ! External analog (analog trigger in) | |
A/D gating modes | External digital: Programmable, active high or active low, level or edge | |
| External analog: | |
| ! Above or below reference | |
| ! Positive or negative hysteresis | |
| ! In or out of window. | |
| Trigger levels set by DAC0 and/or DAC1. | |
A/D trigger sources | ! | External digital (A/D start trigger in and A/D stop trigger in) |
| ! External analog (Analog Trigger In) | |
A/D triggering modes | ! External digital: | |
| ! External analog: | |
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| by DAC0 and/or DAC1. |
| ! | |
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| samples. Compatible with both digital and analog trigger options. |
Data transfer | ! | From 8 k RAM buffer via DMA (demand or |
| ! | Programmed I/O |
Configuration memory | 8 K words | |
Channel/gain queue | Up to 8 K elements. Programmable channel, gain, and offset. | |
A/D conversion time | 500 nS | |
Calibration |