SOYO SY-K7VTA PRO user manual Chipset, Features Dram, Spd

BIOS Setup Utility SY-K7VTA PRO

After you have completed the changes, press [Esc] and follow the instructions on your screen to save your settings or exit without saving. The following table describes each field in the Advanced Chipset Features Menu and how to configure each parameter.

3-4.1 CHIPSET FEATURES SETUP

CHIPSET	Setting	Description	Note
FEATURES
DRAM	Disabled	If enable the DRAM will auto
Timing By	Enabled	detect the DRAM timing	Default
SPD
DRAM Clock	100MHz	This item allows you to control the	Default
	133MHz	DRAM speed.
SDRAM Cycle
	3	When synchronous DRAM is	Default
Length	2	installed, the number of clock
		cycles of CAS latency depends on
		the DRAM timing. Do not reset
		this field from the default value
		specified by the system designer.

Bank Interleave

Disabled Increase DRAM performance. Default

2 Bank

4 Bank

Memory Hole

Disabled		Default
Enabled	Some interface cards will map
	their ROM address to this area. If
	this occurs, select [Enabled] in this
	field.

PCI master Pipeline Req

P2C/C2P Concurrency

Disabled	Disabled/Enabled PCI Master
Enabled	Pipeline Req.	Default
Disabled	This item allows you to
Enabled	enable/disable the PCI to CPU,	Default
	CPU to PCI concurrency.

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