Xilinx XAPP721 manual Reference Design, Read-Enable Logic

Reference Design

R

The ctrl_RdEn signal is required to validate read data because the DDR2 SDRAM devices do not provide a read valid or read-enable signal along with read data. The controller generates this read-enable signal based on the CAS latency and the burst length. This read-enable signal is input to an SRL16 (LUT-based shift register). The number of register stages required to align the read-enable signal to the ISERDES read data output is determined during calibration. One read-enable signal is generated for each data byte. Figure 10 shows the read-enable logic block diagram.

ctrl_RdEn_div0 SRL16

srl_out

FD

ctrl_RdEn

Number of Register Stages

Selected During Calibration

CLKdiv_90

x721_10_113005

Reference Design

iobs

Figure 10: Read-Enable Logic

Figure 11 shows the hierarchy of the reference design. The mem_interface_top is the top-level module. This reference design is available on the Xilinx website at: http://www.xilinx.com/bvdocs/appnotes/xapp721.zip.

		mem_Interface_top
infrastructure			idelay_ctrl			main
				top				test_bench
	user_interface	data_path			ddr2_controller		backend_rom		cmp_rd_data

infrastr_iobs

controller_iobs

datapath_iobs

backend_fifos

rd_data

data_write

tap_logic

addr_gen

data_gen_16

idelay_rd_en_io

v4_dm_iob

v4_dqs_iob

v4_dq_iob

rd_wr_addr_fifo

wr_data_fifo_16

rd_data_fifo

tap_ctrl

data_tap_inc

RAM_D

Figure 11: Reference Design Hierarchy

X721_11_113005

March 2006 Memory Interfaces Solution Guide 65