Xilinx XAPP721 manual Write Data Transmitted Using Oserdes

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Write Datapath

R

Write

Data

Words

0-3

D1
		DQ
D2
D3
D4
		OSERDES
CLKDIV	CLK	CLKdiv_90
		CLKdiv_90
		CLKfast_90
IOB		ChipSyncTM Circuit
		X721_03_080305

Figure 3: Write Data Transmitted Using OSERDES

CLKfast_0

CLKfast_90

Clock Forwarded to Memory Device

Command

WRITE

IDLE

Control (CS_L)

Strobe (DQS)

Data (DQ), OSERDES Output

D0 D1 D2 D3

X721_04_120505

Figure 4: Write Strobe (DQS) and Data (DQ) Timing for a Write Latency of Four

March 2006

Memory Interfaces Solution Guide

57

Image 3

Contents Introduction Clocking Scheme SummaryWrite Datapath Command and Control TimingWrite Data Transmitted Using Oserdes Write Timing Analysis Show the timing relationship Controller to Write Datapath InterfaceWriteidle Read Datapath Read Timing AnalysisRead Datapath Read Timing Analysis at 333 MHz Parameter Value ps Meaning Per Bit Deskew Data Capture TechniqueRead Data and Strobe Delay Controller to Read Datapath Interface Read-Enable Timing for CAS Latency of 5 and Burst LengthReference Design Read-Enable LogicReference Design Utilization ConclusionRevision History