Read Datapath
R
Figure 8 shows the timing waveform for read data and strobe delay determination. The waveforms on the left show a case where the DQS is delayed due to BUFIO and clocking resource, and the ISERDES outputs do not match the expected data pattern. The waveforms on the right show a case where the DQS and DQ are delayed until the ISERDES outputs match the expected data pattern. The lower end of the frequency range useful in this design is limited by the number of available taps in the IDELAY block, the PCB trace delay, and the CAS latency of the memory device.
CLKdiv_0
CLKfast_0
CLKfast_90
CLKdiv_90
DQS @ FPGA |
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DQ @ FPGA |
| D0 D1 D2 D3 |
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DQS @ ISERDES |
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delayed by BUFIO |
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and clocking resource |
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| DQ | D0 D1 D2 D3 |
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| D0 | D2 |
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DQ Captured in DQS Domain |
| D1 | D3 |
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| Input to Q2 Reg | D0 | D2 | D0 | |
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| Input to Q1 Reg |
| D1 | D3 | |
CLKfast_90 |
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Domain | Input to Q4 Reg |
| D0 | D2 | |
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| Input to Q3 Reg |
| D1 | D3 | |
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| Parallel Data @ ISERDES | |||
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| Outputs Q4, Q3, Q2, Q1 | |||
DQS @ FPGA |
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DQ @ FPGA | D0 D1 D2 D3 |
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DQS Delayed by Calibration |
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Delay @ ISERDES |
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DQ Delayed by Calibration Delay D0 D1 D2 D3 | |||
| D0 | D2 | |
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| D1 | D3 |
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| D0 | D2 |
D1 |
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| D1 |
No Match |
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| D0 |
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Incorrect Data |
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| D1 |
Sequence |
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D2,D3,D0,D1 | Parallel Data @ ISERDES | |
Outputs Q4, Q3, Q2, Q1 | ||
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Correct Data Sequence
D3
D2
D3
D0,D1,D2,D3
X721_08_112905
Figure 8: Read Data and Strobe Delay
March 2006 | Memory Interfaces Solution Guide | 63 |