
R
ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a)
ChipScope PLB46 IBA I/O Signals
Table 1: IBA_PLBv46 Pin Descriptions
Port | MU | Signal Name |
| Interface | I/O | Description |
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P1 |
| CONTROL |
| ICON | I/O | Icon control bus IO |
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P2 |
| PLB_Clk |
| System | I | System Clock |
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P3 | MU_1C | iba_trigin_in |
| GENERIC | I | Generic Trigger Inputs |
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P4 |
| iba_trig_out |
| GENERIC | O | IBA Trigger Output |
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| Reset & Error Status |
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P5 | MU_1A | PLB_Rst |
| System | I | Registered reset output from arbitration |
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| logic |
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P6 | MU_1A | Bus_Error_Det |
| System | I | Bus Error Interrupt |
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P7 | MU_1A | PLB_lockErr |
| Slave | I | PLB lock error indicator |
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P8 | MU_1B | PLB_MRdErr[0: |
| Master | I | PLB Master slave read error indicator |
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P9 | MU_1B | PLB_MWrErr[0: |
| Master | I | PLB Master slave write error indicator |
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P10 | MU_1B | PLB_MIRQ[0: |
| Master | I | Master interrupt request. For each master, |
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| indicates when a slave has encountered an |
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| event that is significant to the master |
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P11 | MU_1B | PLB_MTimeout[0: |
| Master | I | PLB |
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| Common Signals |
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P12 | MU_2A | PLB_PAValid |
| Slave | I | PLB primary address valid indicator |
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P13 | MU_2A | PLB_SAValid |
| Slave | I | PLB secondary address |
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P14 | MU_2A | PLB_busLock |
| Slave | I | PLB BusLock |
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P15 | MU_2A | PLB_abort |
| Slave | I | PLB abort bus request indicator |
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P16 | MU_2A | PLB_Swait |
| Simulation | I | Output of Sl_wait OR gate |
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P17 | MU_2A | PLB_SaddrAck |
| Simulation | I | Output of Sl_addrAck OR gate |
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P18 | MU_2A | PLB_Srearbitrate |
| Simulation | I | Output of Sl_rearbitrate OR gate |
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P19 | MU_2A | PLB_RNW |
| Slave | I | PLB read not write |
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P20 | MU_2A | PLB_SwrDAck |
| Simulation | I | Output of Sl_wrDAck OR gate |
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P21 | MU_2A | PLB_SwrComp |
| Simulation | I | Output of Sl_wrComp OR gate |
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P22 | MU_2A | PLB_SwrBTerm |
| Simulation | I | Output of Sl_wrBTerm OR gate |
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P23 | MU_2A | PLB_wrBurst |
| Slave | I | PLB burst write transfer indicator |
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P24 | MU_2A | PLB_SrdDAck |
| Simulation | I | Output of Sl_rdDAck OR gate |
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P25 | MU_2A | PLB_SrdComp |
| Simulation | I | Output of Sl_rdComp OR gate |
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P26 | MU_2A | PLB_SrdBTerm |
| Simulation | I | Output of Sl_rdBTerm OR gate |
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P27 | MU_2A | PLB_rdBurst |
| Slave | I | PLB burst read transfer indicator |
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P28 | MU_2B | PLB_size[0:3] |
| Slave | I | PLB Transfer size |
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P29 | MU_2B | PLB_type[0:2] |
| Slave | I | PLB Transfer type |
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P30 | MU_2B | PLB_MSize[0:1] |
| Slave | I | PLB data bus port width indicator. |
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P31 | MU_2B | PLB_Ssize[0:1] |
| Simulation | I | Output of slave Sl_SSize OR gate |
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P32 | MU_2B | PLB_masterID[0: |
| Slave | I | PLB current master identifier |
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P33 | MU_2B | PLB_BE[0: |
| Slave | I | PLB byte enables |
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DS619 (v1.0) September 17, 2007 | www.xilinx.com |
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Product Specification |
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