Xilinx v1.00a specifications Address, Data, Slave, PLB Arbitration Signals

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ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a)

Table 1: IBA_PLBv46 Pin Descriptions (Continued)

Port

MU

Signal Name

 

Interface

 

I/O

Description

 

 

 

 

 

 

 

 

 

 

P34

MU_2C

PLB_TAttribute[0:15]

 

Slave

 

I

PLB Transfer Attribute

 

 

 

 

 

 

 

 

 

 

 

 

 

Address

 

 

 

 

 

 

 

 

 

 

 

 

P35

MU_3A

PLB_ABus[0:31]

 

Slave

 

I

PLB address bus, lower 32 bits

 

 

 

 

 

 

 

 

 

 

P36

MU_3B

PLB_UABus[0:31]

 

Slave

 

I

PLB address bus, upper 32 bits

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data

 

 

 

 

 

 

 

 

 

 

 

P37

MU_4

PLB_wrDBus[0: C_PLBV46_DWIDTH-1]

Slave

 

I

PLB write data bus

 

 

 

 

 

 

 

 

 

 

P38

MU_5

PLB_SrdDBus[0:

 

Sim

 

I

Output of SL_rdDBus OR gate

 

 

 

C_PLBV46_DWIDTH-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Slave

 

 

 

 

 

 

 

 

 

 

 

 

P39

MU_6A

PLB_rdPrim[0:

 

Slave

 

I

PLB secondary to primary read request

 

 

 

C_PLBV46_NUM_SLAVES-1]

 

 

 

 

indicator

 

 

 

 

 

 

 

 

 

 

P40

MU_6A

PLB_wrPrim[0:

 

Slave

 

I

PLB secondary to primary write request

 

 

 

C_PLBV46_NUM_SLAVES-1]

 

 

 

 

indicator

 

 

 

 

 

 

 

 

 

 

P41

MU_6A

Sl_AddrAck[0:

 

Slave

 

I

Slave Address acknowledge

 

 

 

C_PLBV46_NUM_SLAVES-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P42

MU_6A

Sl_Rearbitrate[0:

 

Slave

 

I

Slave bus re-arbitrate indicator

 

 

 

C_PLBV46_NUM_SLAVES-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P43

MU_6A

Sl_wait[0: C_PLBV46_NUM_SLAVES-1]

Slave

 

I

Slave wait indicator

 

 

 

 

 

 

 

 

 

 

P44

MU_6A

Sl_rdBTerm[0:

 

Slave

 

I

Slave terminate read burst indicator

 

 

 

C_PLBV46_NUM_SLAVES -1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P45

MU_6A

Sl_rdComp[0:

 

Slave

 

I

Slave read transfer complete indicator

 

 

 

C_PLBV46_NUM_SLAVES -1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P46

MU_6A

Sl_rdDAck[0:

 

Slave

 

I

Slave read data acknowledge

 

 

 

C_PLBV46_NUM_SLAVES-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P47

MU_6A

Sl_wrBTerm[0:

 

Slave

 

I

Slave terminate write burst indicator

 

 

 

C_PLBV46_NUM_SLAVES -1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P48

MU_6A

Sl_wrComp[0:

 

Slave

 

I

Slave write transfer complete indicator

 

 

 

C_PLBV46_NUM_SLAVES -1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P49

MU_6A

Sl_wrDAck[0:

 

Slave

 

I

Slave write data acknowledge

 

 

 

C_PLBV46_NUM_SLAVES-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P50

MU_6B

Sl_rdWdAddr[0:

 

Slave

 

I

Slave read word address

 

 

 

C_PLBV46_NUM_SLAVES*4-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P51

MU_6B

Sl_SSize[0:

 

Slave

 

I

Slave data bus port size indicator

 

 

 

C_PLBV46_NUM_SLAVES*2-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P52

MU_7

Sl_MBusy[0: C_PLBV46_NUM_SLAVES

Slave

 

I

Slave busy indicator

 

 

 

*C_PLBV46_NUM_MASTERS-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P53

MU_8

Sl_MRdErr[0:

 

Slave

 

I

Slave read error indicator

 

 

 

C_PLBV46_NUM_SLAVES

 

 

 

 

 

 

 

 

*C_PLBV46_NUM_MASTERS-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P54

MU_9

Sl_MWrErr[0:

 

Slave

 

I

Slave write error indicator

 

 

 

C_PLBV46_NUM_SLAVES

 

 

 

 

 

 

 

 

*C_PLBV46_NUM_MASTERS-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PLB Arbitration Signals

 

 

 

 

 

 

 

 

 

 

 

 

P55

MU_10

M_request[0:

 

Master

 

I

Master bus request

 

 

 

C_PLBV46_NUM_MASTERS-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P56

MU_10

M_priority[0:

 

Master

 

I

Master bus request priority

 

 

 

C_PLBV46_NUM_MASTERS*2-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P57

MU_10

M_busLock[0:

 

Master

 

I

Master Bus Lock

 

 

 

C_PLBV46_NUM_MASTERS-1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DS619 (v1.0) September 17, 2007

www.xilinx.com

 

 

 

Product Specification

 

 

 

 

3

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Contents Introduction FeaturesCommon Signals ChipScope PLB46 IBA I/O SignalsPort Signal Name Interface Description Reset & Error StatusSlave PLB Arbitration SignalsAddress DataMBE0 CPLBV46NUMMASTERS PLB Master SignalsCPLBV46NUMMASTERS*4-1 CPLBV46NUMMASTERS*3-1Value Type ChipScope PLB46 IBA ParametersPLB Address Trigger In, PLB Reset, and PLB Error StatusIBA Storage Options and Trig Out PLB Grouped Control BusSlave Control Bus PLB DataSlave Read/Writer Error Status Slave Busy StatusPLB Arbitration PLB Master Byte Enable Value Type PLB Master Control BusPLB Master Size and Type Status Target Technology ChipScope PLB46 IBA Module Block Diagram RestrictionsDesign Implementation Allowable Parameter Combinations