Clevo D480V manual Lvds Interface SiS302LV, 30 AAD0..15, 30 AAD19..26

Schematic Diagrams

LVDS Interface (SiS302LV)

B.Schematic Diagrams

Sheet 11 of 42 LVDS interface (SiS302LV)

C272

33PF(R)

Y

L68

30

Y

R259

0

1

2

FCM1608K-121T07

JTV2

L69

C

30

C

1

2

4

3

2.7UH

AC

D24

AC

D25

2

1

C275

33PF(R)

R252

C297

C273

DA204U(R)

DA204U(R) R260

75

C300

C276

75

330PF

330PF

C

A

C

A

330PF

330PF

6 5

SVIDEO CON

+3VS

PIN(GND1,GND2)=GND

5

VAGCLK

VAGCLK

T

VBGCLK

VBGCLK

5

5

VAHSYNC

AAD28/VBCTL0 5,30

5

VAVSYNC

VBHSYNC

5

R54

2.2K

LDDCDATA

VBVSYNC

5

+3VS

LDDCCLK

VAVSYNC VAHSYNC DGND AAD15 AAD14 AAD13 AAD12 AAD11 AAD8

DGND DVDD AAD2 AAD3 AAD4 AAD5 AAD6 AAD7 AAD28/VBCTL0 VBHSYNC VBVSYNC

R55

2.2K

5,30 AAD[0..15]

AAD[0..15]

DGND DVDD AAD9 AAD10 AAD26 AAD25 AAD23 AAD24

AAD19 AAD20 AAD22 AAD21 AAD0 AAD1

AAD[19..26]

5,30 AAD[19..26]

102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

U19

VBCAD R332

4.7K(R)

V2/VAVSYNC

H2/VAHSYNC DGND/OVSS D2[11]/VAD11 D2[10]/VAD10

D2[9]/VAD9 D2[8]/VAD8 D2[7]/VAD7 D2[6]/VAD6

XCLK2/VAGCLK DGND/DVSS3 XCLK2*/DVDD3 D2[5]/VAD5 D2[4]/VAD4 D2[3]/VAD3 D2[2]/VAD2 D2[1]/VAD1 D2[0]/VAD0 DVDD/RESERVED

DVDD/RESERVED D1[11]/VBD11 D1[10]/VBD10 D1[9]/VBD9 D1[8]/VBD8 D1[7]/VBD7 D1[6]/VBD6

XCLK1/VBGCLK DGND/DVSS2 XCLK1*/DVDD2 D1[5]/VBD5 D1[4]/VBD4 D1[3]/VBD3 D1[2]/VBD2 D1[1]/VBD1 D1[0]/VBD0 DGND/VBCTL0 H1/VBHSYNC V1/VBVSYNC

+3VS

DVDD

103

DVDD/DVDD4

DVDD1/DVDD

64

DVDD

5,30

AAD16/VADE

AAD16/VADE

104

63

AAD27/VBDE

AAD27/VBDE

5,30

DGND

105

DE2/VADE

VBDE/DE1

62

AAD29/VBCTL1

FLD/STL2/DVSS4

VBCTL1/FLD/STL1

AAD29/VBCTL1 5,30

106

61

DGND

5

VBCAD

T

VBCAD

107

AS/RESERVED

DVSS1/VREF1

60

VDDV

VBHCLK

108

SPD/VBCAD

OVDD/VDDV

59

VBCLK

5

VBHCLK

DGND

109

SPC/VBHCLK

VBCLK/P-OUT

58

DGND

VBCLK 5

DVDD

110

HIN/DVSS5

DVSS0/RESET*

57

VREF2

111

VIN/DVDD5

TVCLKO/GPIO[5]

56

DVDD

T

112

VREF2/OVDD

TSCLKI/GPIO4

55

T

113

SDD/GPIOA(GPI)

DVDD0/TVPLL_VDD

54

TVPLLVDD

114

SDC/GPIOB(GPI)

PLL1VDD/TVPLL_V

53

VBOSCO

T

115

DD1/GPIOC(GPI)

VBOSCO/XO

52

VBRCLK

LDDCDATA

R385

100

116

DC1/GPIOD(GPI)

VBRCLK(XIN)/XIN

51

TVPLLGND

T

LDDCCLK

R386

100

117

DD2/LDDCDATA

PLL1GND/TVPLL_G

50

+5VS

V5V

118

DC2/LDDCCLK

RESERVED/BOC/VS

49

DAC_GND

V5V

119

V5V/V5V

IOCS/C/HSYNC

48

120

HOUT/V2HSYNC

DAC_GND/DAC_GND

47

DAC_VDD

121

VOUT/V2VSYNC

DAC_VDD/DACA3

46

C424

C49

INTA#

HPD/LCDSENSE

RESERVED/DACB3

C

T

9,13,30

INTA#

122

45

PCIRST#

123

HPINT*/INTA#

IOC/DACA2

44

10U/10V(R) 0.1UF

9,13,14,20,22,24,30

PCIRST#

GPIO[0]/EXTRSTN

RESERVED/DACB2

Y

T

124

43

+3VS

GPIO[1]/PFTEST1

IOY/DACA1

125

42

T R719

4.7K

126

GPIO[2]/PFTEST2

RESERVED/DACB1

41

COMPOSITE

T

11,30

ENAVDD

ENAVDD

127

GPIO[3]/PFTESTO

IOCOMP/DACA0

40

V2COMP

T

ENABKL

128

ENAVDD/GPIOG(GP

V2COMP/DACB0

39

DAC_GND

11,30

ENABKL

ENABKL/GPIOH(GP

DAC_GND/DAC_GND

+3VS

L22

VREF2

LVDSPLLVDD/LPLL RESERVED/LPLLCA LVDSPLLVSS/LPLL LAVSS/LGND RESERVED/LL2C

RESERVED/LL2C* LAVDD/LVDD RESERVED/LDC7 RESERVED?LDC7* LAVSS/LGND RESERVED/LDC6

RESERVED/LDC6* LAVDD/LVDD RESERVED/LDC5

RESERVED/LDC5* LVDSPLLVSS/LGND RESERVED/LDC4 RESERVED/LDC4*

LVDSPLLVDD/LVDD LAVDD/LVDD LX3P/LDC3 LX3N/LDC3* LAVSS/LGND LXC1P/LL1C LXC1N/LL1C*

LAVDD/LVDD LX2P/LDC2

LX2N/LDC2*

LAVSS/LGND LX1P/LDC1

LX1N/LDC1*

LAVDD/LVDD LX0P/LDC0

LX0N/LDC0*

LAVSS/LGND EXTSWING/VSWING DACVDD/DACVDD V2RSET/ISET

Spread

FCM1608K121(R)

C67

11,30

LDC2-

LDC2-

range:R120:+-1.5%/+-2.5%

0.1UF

11,30

LDC0-

LDC0-

LDC0+

11,30

LDC0+

LDC1-

Choose clock source:main board/crystal

11,30

LDC1-

LDC1+

R1 :NC/22

11,30

LDC1+

11,30

LDC2+

LDC2+

Y2

LDC3-

SIS302LV(R)

VBOSCO

VBRCLK

11,30

LDC3-

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

LDC3+

R353

10

11,30

LDC3+

LL1C-

LVDD2 LDC3+ -LDC3 LGND LL1C+ -LL1C LVDD2 LDC2+ -LDC2 LGND LDC1+ -LDC1 LVDD2 LDC0+ -LDC0 LGND VSWING VDDDAC ISET

C440

14.318MHZ(R)

C423

11,30

LDC4+

LDC5-

LPLLVDD LPLLCAP LPLLGND LGND LL2C+ -LL2C LVDD1 LDC7+ -LDC7 LGND LDC6+ -LDC6 LVDD1 LDC5+ -LDC5 LGND LDC4+ -LDC4

11,30

LL1C-

LL1C+

11,30

LL1C+

LDC4-

R299

147

22P

22P

11,30

LDC4-

LDC4+

11,30

LDC5-

LDC5+

11,30

LDC5+

LDC6-

11,30

LDC6-

LDC6+

C387

R300

6K

11,30

LDC6+

LDC7-

11,30

LDC7-

LDC7+

NC

LPLLVDD

R48

NC

R301

2K

C349

1UF

11,30

LDC7+

LL2C+

11,30

LL2C+

LL2C-

LVDD1

R47

0

11,30

LL2C-

301LV/302LV:R894/R895

+3VS

L19	LVDD1
FCM1608K121(R)
C52	C386	C385
10U/10V(R)	0.1UF	0.1UF
		LGND

+3VS

L100

LVDD2

FCM1608K121(R)

C348 C384 C383

10U/10V(R) 0.1UF 0.1UF

LGND

+3VS

L15

VDDV

FCM1608K121(R)

C56 C55 10U/10V(R) 0.1UF

+3VS

L121

DVDD

FCM1608K121(R)

	C461		C51	C44
N15	10U/10V(R)		0.1UF	0.1UF
				DGND
+3VS		C409		V2COMP
L93		NC/0.1uF		DAC_VDD
FCM1608K121(R)
	C318	C382		C422
N11	10U/10V(R)	0.1UF		0.1UF
				DAC_GND
+3VS
L111				LPLLVDD
FCM1608K121(R)
C507		C389		C388
0.1UF	N12	10U/10V(R)		0.1UF
			LPLLGND
+3VS
L20				TVPLLVDD
FCM1608K121(R)
C308		C53		C54
0.1UF	N2	10U/10V(R)		0.1UF
				TVPLLGND
+3VS
L18				DVDD
FCM1608K121(R)
	C462		C50	C463
	10U/10V(R)		0.1UF	0.1UF
				DGND

B - 12 LVDS Interface (SiS302LV) (71-D40U0-D03)