
| 
 | Code | Beeps | POST Routine Description | 
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 | 3Ch | 
 | Advanced configuration of chipset | 
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 | registers | 
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 | 3Dh | 
 | Load alternate registers with CMOS | 
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 | values | 
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 | 42h | 
 | Initialize interrupt vectors | 
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 | 45h | 
 | POST device initialization | 
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 | 46h | Check ROM copyright notice | 
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 | 48h | 
 | Check video configuration against CMOS | 
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 | 49h | 
 | Initialize PCI bus and devices | 
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 | 4Ah | 
 | Initialize all video adapters in system | 
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 | 4Bh | 
 | QuietBoot start (optional) | 
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 | 4Ch | 
 | Shadow video BIOS ROM | 
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 | 4Eh | 
 | Display BIOS copyright notice | 
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 | 50h | 
 | Display CPU type and speed | 
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 | 51h | 
 | Initialize EISA board | 
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 | 52h | 
 | Test keyboard | 
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 | 54h | 
 | Set key click if enabled | 
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 | 58h | Test for unexpected interrupts | 
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 | 59h | 
 | Initialize POST display service | 
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 | 5Ah | 
 | Display prompt “Press F2 to enter | 
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 | SETUP” | 
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 | 5Bh | 
 | Disable CPU cache | 
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 | 5Ch | 
 | Test RAM between 512 and 640 KB | 
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 | 60h | 
 | Test extended memory | 
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 | 62h | 
 | Test extended memory address lines | 
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 | 64h | 
 | Jump to User Patch1 | 
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 | 66h | 
 | Configure advanced cache registers | 
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 | 67h | 
 | Initialize Multi Processor APIC | 
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 | 68h | 
 | Enable external and CPU caches | 
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 | 69h | 
 | Setup System Management Mode (SMM) | 
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 | area | 
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 | 6Ah | 
 | Display external L2 cache size | 
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 | 6Bh | 
 | Load custom defaults (optional) | 
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 | 6Ch | 
 | Display  | 
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 | 6Eh | 
 | Display possible high address for UMB | 
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 | recovery | 
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 | 70h | 
 | Display error messages | 
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 | 72h | 
 | Check for configuration errors | 
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 | 76h | 
 | Check for keyboard errors | 
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 | 7Ch | 
 | Set up hardware interrupt vectors | 
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 | 7Eh | 
 | Initialize coprocessor if present | 
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 | 80h | 
 | Disable onboard Super I/O ports and | 
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 | IRQs | 
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 | 81h | 
 | Late POST device initialization | 
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| Chapter 4 | 113 |